Stacked Semiconductor Package with Conductive Pillars for 3D Verification
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Solution Overview
Problem
Current semiconductor packaging methods face challenges in efficiently integrating and testing semiconductor dies at the wafer level, leading to increased costs and reduced yield due to complex interfaces and lack of effective verification methods for 3D packaging and 3DIC devices.
Innovation Solution
A method for manufacturing semiconductor packages that involves dicing semiconductor wafers, testing and selecting known good dies, and using conductive pillars and insulating encapsulation to create a stacked structure with thermal dissipating elements, along with a redistribution circuit structure for electrical connectivity and verification testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level packaging is used to integrate semiconductor dies, then productivity and integration efficiency are improved, but manufacturing complexity and interface complexity increase leading to reduced yield
Solution Approach 1:
The patent segments the semiconductor manufacturing process into distinct phases: wafer-level integration phase and package-level testing phase. By separating these functions, the complex interface issues are isolated to specific stages, allowing for targeted solutions. The wafer level package structure is segmented into multiple layers with standardized interfaces, reducing overall interface complexity while maintaining high integration efficiency.
Solution Approach 2:
The patent introduces intermediate testing and verification structures that act as mediators between the wafer-level integration process and final package testing. These intermediate structures provide standardized interfaces that simplify the integration process while enabling effective verification, thus resolving the contradiction between productivity improvement and complexity increase.
2Adaptability or versatility
If complex 3D packaging structures are implemented, then functionality and integration density are improved, but manufacturing cost increases and yield decreases due to lack of verification methods
Solution Approach 1:
The patent implements preliminary testing and verification methods at intermediate stages of the 3D packaging process, before final assembly. This allows for early detection of defects and reduces the need for expensive rework or scrapping of entire packages. The preliminary verification structures are integrated into the manufacturing flow, enabling cost-effective manufacturing of high-density 3D packages.
Solution Approach 2:
The patent incorporates feedback mechanisms through verification testing that provide real-time information about package integrity and functionality. This feedback enables process adjustment and quality control during manufacturing, reducing waste and improving yield while maintaining high integration density. The feedback loop allows for continuous optimization of the manufacturing process.
3Productivity
If wafer level packaging is used, then manufacturing efficiency is improved, but effective verification and testing methods are lacking reducing reliability
Solution Approach 1:
The patent transitions from traditional 2D wafer testing to 3D verification methods that exploit the vertical dimension of wafer level packages. By implementing testing approaches that access multiple layers and interfaces simultaneously, the patent achieves effective verification while maintaining manufacturing efficiency. The 3D verification structures are designed to be integrated into the wafer level package architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves yield by simplifying the integration process, enhancing thermal management, and enabling effective verification of semiconductor packages, thereby improving the reliability and performance of 3D packaging and 3DIC devices.
Implementation Method 1
enhancing thermal management
Implementation Method 2
insulating encapsulation
Data Source
AI summary
A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.