Stacked Package Interconnects via Additive Manufacturing
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in small form factor packages and systems-in-packages, particularly with traditional package-on-package approaches that are costly and inefficient, and in thermal management using polymer thermal interface materials, which lack the necessary thermal conductivity and adhesion to silicon surfaces.
Innovation Solution
The use of high throughput additive manufacturing for creating substrate integrated posts, integrated heat spreaders, and highly conductive layers on dies, along with additive deposition of interconnects between stacked packages and dies, enables cost-effective and efficient thermal management and mechanical coupling, allowing for the use of solder thermal interface materials and other high conductivity materials without the need for traditional wafer-level backside metallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional package-on-package approach with solder-filled through-mold vias is used, then electrical connections between stacked packages are achieved, but the manufacturing process is complex and throughput is slow due to ball drop requirements
Solution Approach 1:
The patent replaces the mechanical ball drop and reflow process with a direct additive manufacturing process that deposits conductive material through deposited layers and sintering, eliminating the need for spherical solder balls and complex assembly equipment while achieving reliable electrical connections
Solution Approach 2:
The patent changes the manufacturing parameters from traditional soldering temperatures and processes to additive manufacturing parameters including material deposition, layer sintering at controlled temperatures, and in-situ formation of interconnects, enabling higher throughput and flexibility
2Reliability
If copper-plated through-mold vias are used for electrical connections, then electrical connectivity is achieved, but multiple resist lamination steps, lithography, and time-consuming plating steps are required increasing cost and reducing throughput
Solution Approach 1:
The patent replaces the multi-step electroplating process with additive manufacturing that directly deposits conductive material and forms vias through layer-by-layer construction followed by sintering, eliminating resist lamination, lithography, and plating steps
Solution Approach 2:
The patent performs preliminary formation of via structures and conductive pathways during the additive manufacturing process itself, rather than requiring subsequent plating steps, by depositing and sintering conductive material in the desired locations before final assembly
3Reliability
If discrete peripheral interposers with through vias are used, then electrical connections are achieved, but the overall package size increases and additional pick and place assembly steps are required
Solution Approach 1:
The patent merges the interposer function with the substrate by integrating through-substrate vias and conductive pathways directly into the substrate structure, eliminating the need for separate discrete interposer components and reducing overall package footprint
Solution Approach 2:
The substrate is designed to perform multiple functions including mechanical support, electrical interconnection, and thermal management, replacing the specialized function of discrete interposers and reducing the number of components required
4Ease of manufacture
If polymer thermal interface material is used, then ease of assembly is achieved, but thermal conductivity is insufficient for high power segments
Solution Approach 1:
The patent uses composite thermal interface materials that combine polymer matrix with high thermal conductivity fillers such as metal particles or ceramic materials, achieving both ease of assembly and high thermal conductivity for high power applications
Solution Approach 2:
The patent changes the thermal interface material properties by selecting materials with optimized thermal conductivity parameters and adhesion characteristics, transitioning from standard polymer TIM to high-performance composite TIM capable of withstanding high power densities
5Temperature
If solder thermal interface material is used to achieve higher thermal conductivity, then thermal performance is improved, but adhesion to bare silicon is poor requiring die backside metallization which increases complexity and cost
Solution Approach 1:
The patent performs preliminary deposition of adhesion-promoting metallization layers on the die backside during the additive manufacturing process or as a preliminary step, enabling direct solder TIM attachment without requiring complex wafer-level backside metallization
Solution Approach 2:
The patent introduces an intermediary adhesion layer or surface treatment that mediates between the solder thermal interface material and the silicon surface, providing both thermal conductivity and adhesion without requiring full backside metallization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances thermal performance, reduces manufacturing costs, and improves reliability by providing flexible and customizable solutions for thermal interface materials and mechanical coupling, addressing the limitations of traditional methods in small form factor packages and systems-in-packages.
Implementation Method 1
high throughput additive manufacturing for creating substrate integrated posts, integrated heat spreaders, and highly conductive layers on dies
Implementation Method 2
additive deposition of interconnects between stacked packages and dies
Implementation Method 3
highly conductive layers deposited on dies using high throughput additive deposition
Data Source
AI summary
A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.