Stacked Semiconductor Package Alignment Keys for Precise Inspection
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving accurate inspection and alignment due to the complexity of semiconductor chip integration and the need for precise alignment key patterns.
Innovation Solution
The semiconductor package design includes a redistribution substrate with first and second semiconductor chips, each featuring alignment key patterns on their edges, allowing for accurate inspection and alignment through the use of dummy patterns and interconnection layers that facilitate precise positioning and recognition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a stacked configuration, then the functionality and integration density are improved, but the alignment precision and inspection accuracy deteriorate due to the complexity of multi-layer integration
Solution Approach 1:
The patent divides the alignment key structure into multiple segments: a first alignment key on the redistribution substrate, a second alignment key on the first semiconductor chip, and a third alignment key on the second semiconductor chip. This segmentation allows each chip layer to have its own alignment reference, enabling independent alignment verification and improving measurement precision in multi-layer integration
Solution Approach 2:
The patent introduces dummy patterns as intermediary elements between the alignment keys and the semiconductor chip active regions. These dummy patterns serve as mediators that facilitate optical inspection and alignment verification without interfering with the functional areas of the chips, thereby improving inspection accuracy in densely integrated structures
2Measurement precision
If alignment key patterns are placed on the edge regions of interconnection layers, then the alignment and inspection accuracy are improved, but the device complexity increases due to additional patterning and interconnection layer structures
Solution Approach 1:
The patent merges the alignment key function with the edge region structure of the interconnection layers. The first, second, and third alignment keys are formed as part of the interconnection layer edge structures rather than as separate additional components. This merging reduces device complexity by utilizing existing structural elements for dual purposes: electrical interconnection and alignment reference
Solution Approach 2:
The interconnection layer edge regions serve multiple functions: they provide electrical connectivity through the interconnection structures and simultaneously serve as carriers for alignment keys that enable precise inspection and positioning. This multi-functionality reduces the need for separate alignment structures, thereby reducing overall device complexity while maintaining high inspection accuracy
Data Source
AI summary
A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.