Stacked Semiconductor Package With Alignment Keys and Vertical Connectors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in marking visibility, chip alignment accuracy, and thermal radiation efficiency, particularly due to the lack of a second material layer and chip-level alignment keys.
Innovation Solution
Incorporating a second material layer with chip-level alignment keys and vertical connectors, along with a wiring layer, to enhance marking visibility, alignment accuracy, and thermal radiation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a single encapsulation layer is used, then the structure is simple, but marking visibility is poor
Solution Approach 1:
The encapsulation layer is divided into two separate layers: a first encapsulation layer directly covering the semiconductor die, and a second encapsulation layer covering the first encapsulation layer. This segmentation allows the second layer to provide enhanced marking visibility through its distinct material composition and optical properties, while the first layer maintains direct structural support functionality.
Solution Approach 2:
The patent employs different materials for the two encapsulation layers to achieve complementary functions. The first encapsulation layer uses a material optimized for structural support and stress distribution, while the second encapsulation layer uses a material with superior optical contrast properties to enhance marking visibility, creating a composite structure that satisfies multiple requirements simultaneously.
2Manufacturing precision
If conventional alignment methods are used, then the process is simple, but chip alignment accuracy is insufficient
Solution Approach 1:
Alignment keys are integrated directly into the first encapsulation layer, allowing the encapsulation structure itself to provide alignment functionality. The alignment keys extend through the first encapsulation layer and are visible in the second encapsulation layer, enabling self-alignment during the packaging process without requiring external alignment tools or complex positioning mechanisms.
Solution Approach 2:
The alignment keys are pre-formed within the first encapsulation layer before the second encapsulation layer is applied. This preliminary creation of alignment features ensures that accurate alignment can be achieved during subsequent packaging steps, as the keys are already in their final positions and configurations to guide chip placement.
3Loss of energy
If thermal radiation efficiency is not optimized, then the structure remains simple, but heat dissipation is insufficient
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat dissipation by implementing vertically stacked semiconductor dies with through-connectors that extend through multiple encapsulation layers. This vertical dimension provides additional thermal pathways, allowing heat to be conducted from upper dies through intermediate dies and connectors to lower dies and substrate, significantly enhancing overall thermal radiation efficiency.
Solution Approach 2:
The first encapsulation layer serves as a thermal intermediary, containing through-connectors that provide direct thermal conduction pathways between stacked semiconductor dies. These connectors act as thermal mediators, efficiently transferring heat from upper dies through the encapsulation structure to lower dies and ultimately to the substrate, improving heat dissipation without requiring complex external cooling systems.
Data Source
AI summary
An example semiconductor package includes a first encapsulation layer, a plurality of semiconductor dies stacked in a staircase structure on the first encapsulation layer, a second encapsulation layer that covers the plurality of semiconductor dies and the first encapsulation layer, a wiring layer on the second encapsulation layer, and a plurality of first vertical connectors that connect the semiconductor dies with the wiring layer. The first encapsulation layer includes a polymer layer and a metal layer between the polymer layer and the second encapsulation layer.