Stacked Semiconductor Package with Heat Shielded Annealing Bonding
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high-density chip stacking with improved mechanical and electrical reliability, while also reducing the occurrence of failures and increasing process efficiency.
Innovation Solution
A semiconductor package is fabricated using a first semiconductor chip with a single crystalline structure and a second semiconductor chip with a polycrystalline structure, where the second chip is mounted on the first chip using an annealing process, and a molding layer surrounds the second chip. A redistribution substrate and conductive posts are used to connect the chips, and a heat shield layer is incorporated in the second semiconductor substrate to manage thermal energy during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-crystal semiconductor substrates are used for high-density chip stacking, then manufacturing precision is maintained, but thermal energy loss increases and bonding reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating a dual-structure semiconductor substrate where only specific regions (heat shield layers) have modified polycrystalline properties, while other regions maintain single-crystal structure. This localized modification allows thermal energy to be concentrated and retained in specific bonding areas without compromising the overall structural integrity or electrical performance of the entire chip.
Solution Approach 2:
The patent changes the crystal structure parameter from uniform single-crystal to a combination of single-crystal and polycrystalline regions. By controlling the crystallinity parameter in specific layers and regions, the substrate can simultaneously maintain mechanical strength and improve thermal energy retention during the bonding process, directly addressing the contradiction between reliability and energy loss.
2Strength
If annealing process is used to mount second chip on first chip, then bonding strength is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the heat shield layers and polycrystalline regions in the semiconductor substrates before the bonding process. This preparation ensures that when annealing is applied, the thermal energy is already optimally distributed and retained, leading to more effective bonding at lower temperatures and reduced process complexity despite the additional structural preparation.
3Temperature
If heat shield layer is added to semiconductor substrate, then thermal radiation properties are improved, but device complexity increases
Solution Approach 1:
The patent uses composite materials by combining single-crystal semiconductor regions with polycrystalline heat shield layers within the same substrate structure. This composite approach allows the substrate to exhibit both the electrical and mechanical properties of single-crystal materials and the thermal radiation control properties of polycrystalline materials, achieving improved thermal management without requiring entirely separate thermal control components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the reliability and efficiency of semiconductor packaging by reducing thermal energy loss, increasing energy efficiency in the bonding process, and improving thermal radiation properties of the semiconductor package.
Implementation Method 1
a heat shield layer is incorporated in the second semiconductor substrate to manage thermal energy during the bonding process
Implementation Method 2
performing an annealing process to mount the second semiconductor chip on the first semiconductor chip
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.