Stacked Semiconductor Package Antenna for Compact RF Connectivity
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Solution Overview
Problem
Existing semiconductor packages face challenges in integrating antennas for radio signal transmission and reception while maintaining miniaturization and efficient connectivity between semiconductor chips and antennas.
Innovation Solution
A semiconductor package design featuring a lower package with a redistribution structure, a semiconductor chip, and vertical connection conductors, stacked with an upper package containing an antenna structure, including a dielectric layer with active and parasitic antenna patterns, and an antenna ground layer, optimized for vertical spacing and thickness to facilitate efficient radio signal communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an antenna is placed in the integrated circuit packaged device, then radio signal transmission and reception is enabled, but the device size increases and manufacturing complexity increases
Solution Approach 1:
The antenna structure is merged with the package substrate structure. The active antenna patterns and parasitic antenna patterns are formed as conductive layers integrated into the package substrate, eliminating the need for separate antenna components. This merging reduces device complexity while maintaining radio signal transmission capability.
Solution Approach 2:
The package substrate serves multiple functions: it provides mechanical support for the semiconductor chip, enables electrical connections through redistribution structures, and functions as an antenna for radio signal transmission. This multi-functionality eliminates the need for dedicated antenna components, reducing overall device complexity.
2Volume of moving object
If the antenna structure is integrated into the package, then miniaturization is achieved, but signal path length increases affecting radiation characteristics
Solution Approach 1:
The antenna structure utilizes the vertical dimension of the package substrate by forming conductive layers at different heights. The active antenna patterns and parasitic antenna patterns are positioned at different vertical levels, creating a three-dimensional antenna configuration that achieves compact size while maintaining effective signal paths for radiation.
Solution Approach 2:
The antenna conductive layers are nested within the package substrate structure, with conductive layers positioned at different vertical levels. This nesting approach allows the antenna to be compactly integrated into the package volume while maintaining the necessary signal path lengths for effective radiation through the vertical arrangement.
3Volume of moving object
If the distance between active antenna patterns and ground conductive layer is reduced, then package miniaturization is achieved, but antenna radiation characteristics deteriorate
Solution Approach 1:
The antenna structure uses a composite configuration with active antenna patterns, parasitic antenna patterns, and ground conductive layers arranged in specific vertical relationships. The parasitic antenna patterns act as intermediate elements that enable compact spacing while maintaining radiation performance, creating a composite antenna system that overcomes the trade-off between size and performance.
Solution Approach 2:
The invention changes the spatial arrangement parameters by positioning conductive layers at specific vertical intervals. The distance between the active antenna patterns and ground conductive layer is optimized at 100-600 micrometers, and the second molding layer thickness is controlled at 50-400 micrometers, creating a parameter-optimized compact structure that maintains radiation characteristics.
Data Source
AI summary
A semiconductor package includes: a lower package; and an upper package stacked on the lower package, wherein the lower package includes: a first redistribution structure; a semiconductor chip mounted on the first redistribution structure; a first molding layer surrounding the semiconductor chip on the first redistribution structure; and first vertical connection conductors disposed on the first redistribution structure and vertically passing through the first molding layer, wherein the upper package includes: a second molding layer disposed on the lower package; second vertical connection conductors vertically passing through the second molding layer and electrically connected to the first vertical connection conductors; and an antenna structure disposed on the second molding layer.