3D Stacked Semiconductor Package with Redistribution and Backside Wiring
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving optimal package performance and size due to spatial limitations and difficulties in mounting semiconductor chips with a large number of I/O terminals or compact sizes directly on electronic device mainboards, particularly with fan-in packages which require redistribution techniques that still fall short in accommodating diverse chip configurations.
Innovation Solution
A semiconductor package structure is proposed, where a first semiconductor chip with a through-via is stacked vertically with a second semiconductor chip, both connected via a redistribution layer and backside wiring layer, allowing for improved power transfer and signal connectivity, and optionally including a third semiconductor chip for memory functions, enabling efficient 3D interconnection and reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips with large number of I/O terminals or compact sizes are mounted directly on mainboards, then package size is reduced, but mounting difficulty and reliability deteriorate
Solution Approach 1:
The patent introduces an intermediate substrate that acts as a mediator between the semiconductor chip and the mainboard. This substrate provides a buffer for signal redistribution and mechanical support, enabling reliable connection of compact chips with large I/O terminals to the mainboard while maintaining a reduced overall package size.
Solution Approach 2:
The patent employs three-dimensional stacking architecture where multiple semiconductor chips are vertically stacked and connected through through-vias. This dimensional transition from planar to vertical arrangement reduces the footprint area while maintaining reliable electrical connections through the stacked structure.
2Adaptability or versatility
If fan-in packages with redistribution techniques are used, then I/O terminal connectivity is improved, but package complexity increases
Solution Approach 1:
The patent divides the redistribution function into separate modular components: the intermediate substrate handles signal redistribution, while the semiconductor chip maintains its original I/O configuration. This segmentation allows flexible I/O connectivity without increasing the complexity of the chip itself, as the redistribution logic is externalized to the substrate layer.
3Volume of moving object
If multiple semiconductor chips are stacked vertically, then package thickness is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary positioning structures such as alignment marks, positioning protrusions, and positioning recesses that are pre-formed on the intermediate substrate and semiconductor chips. These preliminary features guide the vertical stacking process, ensuring precise alignment and reducing the manufacturing precision requirements during the actual assembly operation.
Data Source
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Figure 3A~3B
AI summary
Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.