Stacked Semiconductor Package Bonded Pad Structure for Reliable Interconnects

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving high integration and high-speed performance while maintaining operation reliability, particularly in stacked semiconductor chip configurations.

Innovation Solution

The semiconductor package design includes a first semiconductor chip with penetrating electrodes and bonded pads that connect to stacked second semiconductor chips, featuring rear and front surface cover layers and alignment patterns, allowing for improved electrical connections and reliability through specific structural configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If semiconductor chips are stacked to achieve high integration and miniaturization, then the functionality and performance are improved, but the operation reliability deteriorates due to increased complexity of inter-chip connections

Engineering Contradiction:

Improvehigh integrationVSAvoidoperation reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The bonded pad is divided into multiple segments: a first bonded pad portion in the first cover layer, a second bonded pad portion in the second cover layer, and optionally a third bonded pad portion in the interposer. This segmentation allows each portion to be optimized for its specific function and location, improving overall connection reliability while maintaining high integration

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bonded pad extends in the vertical dimension across multiple layers (first cover layer, interposer, second cover layer) rather than being confined to a single plane. This three-dimensional configuration enables robust inter-chip connections while accommodating the stacked architecture for high integration

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the bonded pad height is increased to ensure robust electrical connections through thicker cover layers, then the connection reliability is improved, but the manufacturing complexity increases

Engineering Contradiction:

Improveconnection reliabilityVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The bonded pad height is precisely controlled within a specific range (equal to or greater than the sum of cover layer thicknesses, and equal to or less than twice the sum of alignment pattern thicknesses). This parameter optimization ensures reliable electrical connections through adequate penetration while preventing excessive complexity in manufacturing and assembly

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If the bonded pad height is decreased to simplify manufacturing, then the manufacturing complexity is reduced, but the electrical connection robustness deteriorates

Engineering Contradiction:

Improvemanufacturing complexityVSAvoidelectrical connection robustness

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The bonded pad height is set to a minimum threshold (equal to or greater than the sum of the thickness of the first rear surface cover layer and the thickness of the second front surface cover layer). This ensures the bonded pad sufficiently penetrates both cover layers to establish robust electrical connections, while avoiding excessive height that would complicate manufacturing

Inventive Principle:

Principle #35Parameter changes

4Volume of moving object

If alignment patterns are placed closer together to reduce package size, then the miniaturization is improved, but the alignment precision during bonding deteriorates

Engineering Contradiction:

Improvepackage sizeVSAvoidalignment precision

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

Alignment patterns are pre-formed on the cover layers and interposer before the bonding process. These patterns serve as predetermined guides that facilitate precise alignment during chip stacking, enabling miniaturization without sacrificing alignment accuracy

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The alignment function is achieved through optical or visual recognition of patterns rather than purely mechanical positioning systems. This allows for higher precision alignment in a compact configuration, as pattern recognition can achieve sub-micron accuracy without requiring large mechanical adjustment mechanisms

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11749662B2Semiconductor package

Publication Date: 2023.09.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.