Stacked Semiconductor Package Bonding Pads for Lower Thermal Resistance
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration, speed, and bandwidth due to limitations in connecting multiple semiconductor chips efficiently.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip stacked with multiple second semiconductor chips, connected through bonding pads with a through via portion and a bonding insulation material layer, where the bonding pads have a specific horizontal width and thickness configuration to enhance electrical and thermal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked to increase integration and bandwidth, then the degree of integration and speed are improved, but thermal resistance increases and thermal management becomes more difficult
Solution Approach 1:
The bonding pad structure is segmented into multiple functional portions: a pad portion for electrical connection, a through via portion for vertical conductivity, and a bonding pad portion for thermal dissipation. This segmentation allows each portion to optimize its specific function while working together to reduce overall thermal resistance in the stacked chip configuration.
Solution Approach 2:
The bonding pad extends in the vertical dimension through the substrate with a through via portion, transforming a traditionally two-dimensional pad structure into a three-dimensional structure. This vertical extension provides additional thermal conduction pathways through the substrate thickness, effectively reducing thermal resistance in the stacked chip arrangement.
2Reliability
If bonding pads are made larger to improve electrical connectivity, then electrical connection is enhanced, but the area available for other components and routing is reduced
Solution Approach 1:
The bonding pad is divided into functionally distinct portions: the pad portion on the first surface provides electrical connection, while the through via portion extends vertically through the substrate. This segmentation allows the electrical connection function to be distributed across multiple spatial locations, reducing the footprint required on any single surface.
Solution Approach 2:
By extending the bonding pad functionality into the vertical dimension through the substrate, the structure provides enhanced electrical connectivity without proportionally increasing the horizontal footprint. The through via portion utilizes the vertical space within the substrate to achieve improved electrical connection while preserving surface area for other components.
3Manufacturing precision
If through via portions with smaller horizontal width are used, then manufacturing precision is improved, but the horizontal width of the pad portion must be larger to maintain electrical connectivity
Solution Approach 1:
The bonding pad structure separates the alignment-critical through via portion from the connection-critical pad portion. The through via portion can be manufactured with smaller, more precise dimensions for better alignment, while the pad portion on the surface can be larger to ensure reliable electrical connection. This segmentation allows independent optimization of each portion's dimensions.
Solution Approach 2:
The through via portion utilizes the vertical dimension to provide electrical connectivity, allowing its horizontal width to be minimized for manufacturing precision without compromising overall connection reliability. The pad portion compensates on the horizontal plane, creating a balanced structure that optimizes both precision and connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical and thermal connectivity, reducing thermal resistance and enhancing the overall performance and integration of the semiconductor package.
Implementation Method 1
a bonding insulation material layer disposed between the first semiconductor chip and the second semiconductor chip
Implementation Method 2
a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip
Data Source
AI summary
A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.