Stacked Semiconductor Package Layout for Shorter Bonding Wires
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Solution Overview
Problem
The challenge of efficiently placing multiple semiconductor chips within a limited package area while minimizing the length of bonding wires in multi-chip type semiconductor packages is not adequately addressed by existing technologies.
Innovation Solution
A semiconductor package design that stacks semiconductor chips in a cascade configuration, utilizing dummy pads and wires to connect signal pads in a one-to-one basis, reducing the need for direct bonding wires between certain chips and shortening the overall wire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked in a multi-chip package, then the number of chips per package is increased, but the bonding wire length increases and package thickness increases
Solution Approach 1:
The patent transitions from a planar chip arrangement to a three-dimensional stacked configuration, allowing multiple chips to be integrated within a limited footprint area. By stacking chips vertically on the package substrate, the system achieves higher chip density without proportionally increasing bonding wire length, as wires connect adjacent stacked chips rather than spanning across a large planar area.
Solution Approach 2:
The patent introduces dummy pads as intermediary connection points between signal pads of different chips. These dummy pads act as mediators that enable indirect signal routing through the package substrate, allowing optimization of wire paths and reduction of direct long-distance wire connections between distant signal pads on different chips.
2Quantity of substance
If multiple semiconductor chips are stacked in a multi-chip package, then the number of chips per package is increased, but the package thickness increases
Solution Approach 1:
The patent utilizes vertical stacking in the thickness dimension to achieve high chip density. By arranging chips in multiple layers stacked on the package substrate and connecting them through vertical wire bonds, the system packs more chips into a compact volume, accepting increased thickness as a necessary trade-off for achieving high integration density in a small footprint.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple chips are stacked and interconnected through the package substrate. Each chip layer is nested within the overall package structure, with wiring layers and dummy pads embedded between and around the chips, creating a compact nested arrangement that maximizes space utilization.
3Speed
If dummy pads and indirect wire connections are used, then wiring complexity increases, but signal processing speed improves
Solution Approach 1:
The patent employs dummy pads as intermediary connection points that facilitate optimized signal routing. These dummy pads serve as intermediate stops in the signal path, allowing signals to be routed through shorter wire segments via the package substrate rather than requiring direct long-distance connections between distant signal pads on different chips, thereby improving signal speed despite added routing steps.
Solution Approach 2:
The patent divides the wiring system into multiple segments, with separate wiring layers for different signal paths and dedicated wire segments connecting specific signal pads through dummy pads. This segmentation allows independent optimization of each wire segment length and routing path, enabling shorter individual wire segments that improve signal processing speed while managing overall wiring complexity through systematic organization.
Data Source
AI summary
A semiconductor device includes a package substrate including substrate pads and a first, second, and third semiconductor chips sequentially stacked on the package substrate. The first semiconductor chip includes first signal pads and first dummy pads in a line, the second semiconductor chip includes second signal pads and third signal pads disposed in a line, the third semiconductor chip includes fourth signal pads disposed in a line. The first signal pads correspond to the second signal pads, the first dummy pads correspond to the third signal pads, the third signal pads correspond to the fourth signal pads, on a one-to-one basis.