Stacked Semiconductor Package Layout for Higher Wafer Bonding Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The wafer-to-wafer bonding process in semiconductor manufacturing often results in reduced bonding yield due to limited bonding interfaces, particularly when stacking multiple semiconductor chips.
Innovation Solution
A semiconductor package design with a stacked structure of multiple chips, where each chip has specific insulation layers and bonding pads, allowing for direct bonding between substrates and through electrodes, enhancing the bonding interface and yield through Cu—Cu Hybrid Bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer-to-wafer bonding process is used to stack multiple semiconductor chips, then the multi-chip package structure is formed, but the bonding yield is reduced due to limited bonding interfaces
Solution Approach 1:
The patent divides the bonding process into multiple stages: first bonding the first semiconductor chip to the substrate, then bonding the second semiconductor chip to the first chip. This segmentation allows each bonding interface to be optimized independently, improving overall bonding yield despite the complexity of stacking multiple chips.
Solution Approach 2:
The patent utilizes both front surfaces and backside surfaces of semiconductor chips for bonding operations. By bonding the second chip's front surface to the first chip's backside surface, and subsequently bonding additional chips to the second chip's backside surface, the patent expands the bonding interfaces into three-dimensional space, effectively increasing the number of available bonding areas.
2Adaptability or versatility
If multiple semiconductor chips are stacked to form multi-chip package, then the functional integration is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary bonding of the first semiconductor chip to the substrate before subsequent bonding operations. This preliminary action establishes a stable foundation and allows for proper alignment and positioning of subsequent chips, simplifying the overall manufacturing process despite the multiple stacking steps required for high functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the bonding yield and process efficiency by creating a thin, stacked semiconductor package with enhanced bonding interfaces, enabling effective face-to-face and backside bonding of chips, thus improving the overall manufacturing yield.
Implementation Method 1
A backside of the third substrate is arranged to face the backside surface of the second substrate such that the third substrate and the second backside insulation layer are bonded directly to each other
Implementation Method 2
A backside of the third substrate is arranged to face the front surface of the second substrate such that the third substrate and the second front insulation layer are bonded directly to each other
Data Source
AI summary
A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.