Stacked Semiconductor Package Bonding With Single-Body Bump Interfaces

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor packaging technologies face challenges in reducing the size and weight of electronic components while maintaining good electrical characteristics, especially for high-frequency signal processing, and achieving structural stability in vertically-stacked integrated circuits.

Innovation Solution

A semiconductor package design featuring a first redistribution substrate with a first die, a second redistribution substrate, and a molding portion, where the second redistribution substrate includes an insulating and conductive pattern, and the conductive patterns on both substrates form a single body with the bumps to enhance structural stability and facilitate bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If multiple semiconductor chips are mounted in a single package to reduce size and weight, then the packaging density increases, but the structural stability and electrical characteristics deteriorate

Engineering Contradiction:
Improvepackage sizeVSAvoidstructural stability
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The package structure is segmented into multiple functional layers including first and second redistribution substrates, device layers with dies, and molding portions. Each layer performs specific functions and is independently structured, allowing for optimized mechanical support and electrical connectivity while maintaining compact overall dimensions

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The redistribution substrates employ composite structures combining insulating patterns and conductive patterns. The conductive patterns are formed of the same material as the bumps to create single-body structures, while insulating materials provide mechanical support and electrical isolation, achieving both compactness and structural stability

Inventive Principle:
Principle #40Composite materials

2Volume of moving object

If multiple semiconductor chips are mounted in a single package to reduce size and weight, then the packaging density increases, but the electrical characteristics deteriorate

Engineering Contradiction:
Improvepackage sizeVSAvoidelectrical characteristics
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The electrical connectivity path is segmented into multiple controlled interfaces: bump-conductive pattern interfaces, via-circuit layer interfaces, and substrate-die interfaces. Each interface is independently optimized with matching materials and controlled impedance designs to maintain signal integrity in high-frequency applications

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conductive patterns in the redistribution substrates are formed of the same material as the bumps to create homogeneous single-body structures. This material homogeneity eliminates interface resistance and ensures consistent electrical characteristics across all connection points

Inventive Principle:
Principle #33Homogeneity

3Volume of moving object

If vertically-stacked integrated circuits are implemented to reduce component size, then the packaging density increases, but the bonding reliability deteriorates

Engineering Contradiction:
Improvepackage sizeVSAvoidbonding reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The bump and conductive pattern are merged into a single-body structure through material continuity. This eliminates the traditional interface between separate bump and substrate conductive elements, creating a unified bonding structure that enhances mechanical strength and electrical reliability in vertically-stacked configurations

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240404972A1Semiconductor package and method of manufacturing the same
Publication Date: 2024.12.05 SAMSUNG ELECTRONICS CO LTD
  • US20240404972A1 patent drawing
  • US20240404972A1 patent drawing
  • US20240404972A1 patent drawing

AI summary

A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.