Stacked Semiconductor Package with Bumpless Bonding Stability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, high capacity, and miniaturization while maintaining structural stability and production yield, particularly in stacked semiconductor chips with through-silicon vias.
Innovation Solution
A semiconductor package design featuring a bumpless bonding structure with a dielectric layer covering the side surfaces of semiconductor chips and through-vias penetrating through the dielectric layer to connect pads, enhancing structural stability and production yield by eliminating the need for adhesive and connecting members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bonding structures with adhesive and connecting members are used, then assembly is straightforward, but chip shifting occurs during electrical testing reducing production yield
Solution Approach 1:
The patent removes adhesive and connecting members from the bonding structure, extracting the problematic elements that caused chip shifting. The direct bonding interface between chips eliminates the need for intermediate bonding materials, thereby preventing shifting during electrical testing and improving production yield.
Solution Approach 2:
The patent merges the bonding function and electrical connection function into a single integrated structure. The bumpless bonding interface directly connects chips without separate adhesive layers or connecting members, simplifying the overall structure while maintaining both mechanical bonding and electrical connectivity.
2Reliability
If stacked semiconductor chips with through-silicon vias are implemented, then high performance and high capacity are achieved, but structural stability becomes difficult to maintain
Solution Approach 1:
The patent performs preliminary bonding between chips before final assembly, creating a stable bonded structure in advance. The bumpless bonding process establishes strong mechanical bonds between stacked chips prior to subsequent assembly steps, ensuring structural stability is maintained throughout the manufacturing process and final product.
3Productivity
If bumpless bonding structure is used, then chip shifting is prevented improving production yield, but additional dielectric layer processing is required
Solution Approach 1:
The dielectric layer is segmented into multiple regions with different functions: a first region covering the side surface of the chip and a second region filling the space between chips. This segmentation allows each region to be optimized for its specific purpose while being formed through an integrated process flow that doesn't significantly complicate manufacturing.
Solution Approach 2:
The dielectric layer serves multiple functions simultaneously: it provides electrical insulation, fills gaps between chips, supports the bonding interface, and enables through-via formation for electrical connections. This multi-functionality reduces the need for separate processing steps for each function.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and including a through-silicon via electrically connecting a front pad and a rear pad, a dielectric layer having a first region covering a side surface of the second semiconductor chip and a second region filling space between the first semiconductor chip and the second semiconductor chip, a first through-via penetrating through the first region of the dielectric layer, and a second through-via penetrating through the second region of the dielectric layer.