Stacked Semiconductor Package Layout for Dense Chip Interconnects
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Solution Overview
Problem
There is a challenge in efficiently placing and connecting semiconductor chips within limited package areas to achieve miniaturization and lightweight electronic components while maintaining reliable electrical characteristics.
Innovation Solution
The semiconductor package design includes a package substrate with stacked semiconductor chip stacks, input/output signal bumps, and wire bonding pads connected by wires and balls, optimizing signal and power distribution to enhance packing efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of semiconductor chips in the package is increased, then the packing density is improved, but the available area for placing and connecting chips is reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of chips to a three-dimensional stacked configuration. Multiple chip stacks are vertically arranged on the package substrate, with each stack containing multiple chips connected through bumps and wires. This vertical stacking enables significantly higher chip density within the same footprint area, directly resolving the contradiction between increasing chip quantity and maintaining available package area.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked vertically to form chip stacks, and multiple such stacks are arranged on the package substrate. Each chip stack nests chips one above another, with connection structures (bumps and wires) nesting within the vertical space between chips. This nested arrangement maximizes the use of three-dimensional space, allowing more chips to be packaged without increasing the horizontal footprint.
2Area of moving object
If the size of semiconductor chips is increased, then the functional capability is improved, but the number of chips that can be accommodated in the package is reduced
Solution Approach 1:
By arranging chips in vertical stacks rather than horizontal layouts, the patent allows larger individual chip sizes while maintaining high overall chip counts. The vertical dimension provides additional space that does not consume horizontal package area, enabling each chip to be larger without reducing the total number of chips that can be accommodated in the package volume.
3Length of moving object
If wire bonding pads are disposed closer to input/output signal bumps, then the wire length is reduced, but the signal interference between wire and ball increases
Solution Approach 1:
The patent applies different spatial arrangement strategies to different functional regions. In regions where wires connect to bumps, the bonding pads are positioned to minimize wire length. In regions where balls connect to bumps, the bonding pads are positioned to maintain adequate spacing and avoid interference. This localized optimization of pad positions resolves the contradiction by adapting the arrangement to the specific functional requirements of each connection type.
4Weight of stationary object
If the package area is reduced for miniaturization, then the weight and size of electronic components are reduced, but the reliability of electrical connections may be compromised
Solution Approach 1:
The vertical stacking architecture reduces the horizontal footprint and overall package size while maintaining robust electrical connections through multiple vertical connection points (bumps and wires). The three-dimensional arrangement provides redundant connection paths and shorter current paths, which can actually improve reliability despite the reduced package size.
Solution Approach 2:
The patent merges multiple connection functions into integrated structures. The bumps serve both as mechanical support and electrical connections, while the wires provide both structural integrity and electrical pathways. This merging of functions within compact structures maintains reliability while reducing package size and weight.
Data Source
AI summary
A semiconductor package includes a package substrate. A lower chip is on the package substrate. An upper chip is on the lower chip. An input/output signal bump is between the lower chip and the package substrate and receives/outputs a signal to/from the lower chip. A wire bonding pad is on the upper chip and includes a wire connected thereto. A first input/output signal ball is on the package substrate and receives/outputs the signal to/from the lower chip and is connected to the input/output signal bump. A second input/output signal ball is on the package substrate and receives/outputs a signal to/from the upper chip and is electrically connected to the wire bonding pad. The input/output signal bump is closer to the first input/output signal ball than the second input/output signal ball. The wire bonding pad is closer to the second input/output signal ball than the first input/output signal ball.