Stacked Package Interconnect Using Conductive Bumps Under Thermal Stress
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Solution Overview
Problem
Conventional package on package (PoP) technology experiences structural damage and electrical transmission issues due to voids in conductive pillars formed by electroplating, and separation of encapsulant from substrates with different thermal expansion coefficients under thermal stress.
Innovation Solution
A stacked package device using conductive bumps to electrically connect substrates without encapsulant, utilizing solid metal bumps or metal core with conductive layers to prevent thermal stress damage and maintain structural integrity, with underfill to protect and support the bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive pillars are formed by electroplating process, then electrical connection between substrates is achieved, but voids are formed in the conductive pillars causing structural damage and electrical transmission deterioration under thermal stress
Solution Approach 1:
The invention extracts and eliminates the problematic electroplating process and encapsulant from the package structure. By removing the electroplating step, void formation is prevented. By removing the encapsulant, thermal stress-induced separation is eliminated. The design uses direct bonding of substrates with conductive bumps instead, achieving electrical connection without the harmful intermediate elements.
Solution Approach 2:
The invention changes the manufacturing parameter from electroplating to direct metal bump formation or sintering. This parameter change eliminates void formation inherent in electroplating. Additionally, the removal of encapsulant changes the thermal expansion parameter of the overall structure, eliminating CTE mismatch issues between encapsulant and substrates.
2Volume of stationary object
If encapsulant is provided to fill space between substrates, then space utilization is improved, but separation between encapsulant and substrates occurs under thermal stress due to different coefficients of thermal expansion
Solution Approach 1:
The invention completely removes the encapsulant from the package structure. By extracting this problematic component, the issue of thermal expansion mismatch and subsequent separation is eliminated. The space previously occupied by encapsulant is now filled with underfill material that has compatible thermal properties or is applied only where needed for chip support.
3Adaptability or versatility
If conventional PoP structure with encapsulant and conductive pillars is used, then multiple packages can be stacked, but thermal stress causes both void damage to conductive pillars and separation of encapsulant from substrates
Solution Approach 1:
The invention extracts and removes both the electroplating process and the encapsulant from the stacked package structure. This dual removal eliminates the two main sources of thermal stress damage: voids in conductive pillars and encapsulant separation. The resulting structure uses direct substrate bonding with conductive bumps, maintaining stacking capability while dramatically improving thermal stress resistance.
Data Source
AI summary
A stacked package device has a first package and a second package vertically stacked and electrically connected to each other. One or each of the first package and the second package includes a first substrate, a second substrate and multiple conductive bumps. A first flip-chip and a second flip-chip are respectively mounted on opposite surfaces of the first substrate and the second substrate. The multiple conductive bumps are electrically connected between the opposite surfaces of the first substrate and the second substrate to achieve signal transmission between the first flip-chip and the second flip-chip. The use of the multiple conductive bumps avoids the structure damage resulting from thermal stress. Since no encapsulant is provided to cover each flip-chip, the problem of separation between the encapsulant and the substrate is avoided.