Stacked Semiconductor Package With Conductive Post Power Path
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Solution Overview
Problem
Current semiconductor packages face challenges in enhancing electrical properties and reliability, particularly in connecting semiconductor chips efficiently while maintaining durability.
Innovation Solution
A semiconductor package design featuring a substrate with a first semiconductor chip, a second semiconductor chip, and a conductive post that directly connects the second chip to the substrate, bypassing the first chip, along with a redistribution substrate and molding layers for improved electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure is used with bonding wires or bumps to electrically connect the semiconductor chip to the printed circuit board, then the package can be manufactured with standard processes, but the electrical properties such as resistance and power integrity are limited
Solution Approach 1:
The patent introduces a vertical stacking architecture where semiconductor chips are arranged in multiple layers and connected through via holes. This three-dimensional configuration transforms the conventional planar two-layer structure into a multi-layer vertical architecture, enabling shorter electrical paths and improved power integrity by reducing the distance between power delivery and consumption points.
Solution Approach 2:
The patent divides the semiconductor package into multiple independent chips stacked vertically, each chip being separately manufactured and then interconnected through via holes. This segmentation allows for modular design, independent chip optimization, and flexible assembly, while the via holes provide direct electrical connections that bypass conventional bonding structures.
2Reliability
If the second semiconductor chip is directly connected to the substrate through a conductive post bypassing the first chip, then the voltage supply path is lengthened and power integrity is improved, but the device structure becomes more complex
Solution Approach 1:
The patent introduces via holes as intermediary conductive structures that penetrate through the substrate and intermediate layers to establish direct electrical connections. These via holes act as mediators that enable the second semiconductor chip to connect directly to the substrate's power supply, creating extended voltage supply paths that improve power integrity while maintaining a systematic fabrication process.
3Reliability
If multiple semiconductor chips are stacked vertically with direct bonding pad contact, then the electrical connectivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the electrical connection function from the bonding pad interface and relocates it to via holes that penetrate through the substrate. By taking out the direct bonding pad-to-bonding pad contact requirement and replacing it with via hole-mediated connections, the design reduces the stringent alignment precision requirements while maintaining improved electrical connectivity through the vertical stacking architecture.
Data Source
AI summary
Disclosed is a semiconductor package including a substrate, a first semiconductor chip on the substrate and including a through via in the first semiconductor chip and a plurality of first bonding pads on an upper portion of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a plurality of second bonding pads on a lower portion of the second semiconductor chip, and a conductive post between a top surface of the substrate and a bottom surface of the second semiconductor chip and laterally spaced apart from the first semiconductor chip. The first bonding pads are in contact with the second bonding pads. A width in a first direction parallel to a plane defined by a bottom surface of the substrate of the second semiconductor chip is greater than a width in the first direction of the first semiconductor chip.