Stacked Semiconductor Package With Conductive Posts for Small-Chip Mounting
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Solution Overview
Problem
Existing semiconductor packages face challenges with small semiconductor chips, such as adherence and handling of solder balls, and require various mount boards due to varying chip sizes, necessitating improved structural stability and manufacturing processes.
Innovation Solution
A semiconductor package design featuring a stacked chip structure with insulating patterns, conductive posts, and connection wires, along with a molding layer and package substrate, ensuring stable electrical connections and simplified manufacturing through a method involving attachment, bonding, and molding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are made smaller for high integration, then the integration density is improved, but the adherence and handling of solder balls becomes difficult
Solution Approach 1:
The patent extracts the solder ball attachment function from the chip surface and relocates it to the mount board. By forming conductive posts and mounting pads on the mount board, the solder balls are attached to the board rather than directly to the small chip, making adherence and handling easier while maintaining high integration density through vertical stacking
Solution Approach 2:
The patent transitions from a planar 2D arrangement to a 3D vertical stacking configuration. Multiple semiconductor chips are stacked vertically on the mount board, allowing high integration density without requiring smaller chip sizes, thus avoiding the solder ball adherence problem
2Adaptability or versatility
If various sizes of semiconductor chips are used, then the adaptability to different applications is improved, but the requirement for various mount boards increases
Solution Approach 1:
The mount board is designed with universal mounting structures including conductive posts and mounting pads that can accommodate semiconductor chips of various sizes. The insulating pattern and conductive post configuration allow different chip sizes to be mounted on the same board type, reducing the need for multiple specialized mount boards while maintaining adaptability to different applications
3Quantity of substance
If a stacked chip structure is implemented, then the integration density is improved, but the structural stability becomes challenging
Solution Approach 1:
The patent introduces an insulating pattern as an intermediary element between the conductive posts and the semiconductor chips. This insulating pattern provides mechanical support and electrical isolation, enhancing the structural stability of the stacked configuration while enabling high integration density. The insulating pattern also helps distribute mechanical stresses across the stack
Data Source
AI summary
A semiconductor package may include a first semiconductor chip including a first chip pad on an upper surface of the first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip and including a second chip pad on an upper surface of the second semiconductor chip, an insulating pattern covering a side surface of the first semiconductor chip and having a width that decreases from a lower surface of the first semiconductor chip toward the upper surface of the first semiconductor chip, a conductive post at one side of the second semiconductor chip, the conductive post connected to the first chip pad and extending in a direction perpendicular to the upper surface of the first semiconductor chip, a seed pattern between the first chip pad and the conductive post, and a first connection wire connected to the second chip pad.