Stacked Semiconductor Package Corner Frames for Crack Isolation
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, high performance, and reliability due to issues like cracking, electrical shorts, and detachment between stacked semiconductor chips.
Innovation Solution
A semiconductor package design featuring a plurality of semiconductor chips stacked with bumps on their surfaces, surrounded by an underfill layer and spaced insulating frames that overlap corner regions, enhancing the reliability of the front or rear surfaces by preventing cracking, electrical shorts, and warpage, and improving the integration of bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in multiple stages to achieve miniaturization and high capacity, then the density and capacity of the package are improved, but the reliability deteriorates due to cracking, electrical shorts, and detachment between chips
Solution Approach 1:
The patent introduces insulating frames that divide the package structure into multiple regions, creating physical segments between stacked chips. These frames are positioned at corner regions and extend in vertical directions, effectively segmenting the package to prevent propagation of cracks and electrical shorts across the entire chip stack, thus resolving the reliability issue while maintaining high stacking capacity
Solution Approach 2:
The insulating frames act as intermediary elements between adjacent chips in the stacked configuration. These frames provide mechanical support and electrical isolation, serving as mediators that prevent direct contact between chips at corner regions, thereby preventing detachment and electrical shorts while allowing the chips to maintain their stacked arrangement for high capacity
2Reliability
If insulating frames are added to prevent cracking and detachment, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The insulating frames are strategically positioned only at corner regions of the package rather than covering the entire chip surfaces. This localized approach provides the necessary mechanical support and electrical isolation at the most critical stress points where cracks and detachment are most likely to occur, while minimizing the overall addition to device complexity by avoiding unnecessary frames in less critical areas
3Reliability
If multiple bumps are disposed on chip surfaces for electrical connection, then the electrical performance is improved, but the risk of electrical shorts and cracking increases
Solution Approach 1:
The insulating frames serve as intermediary barriers between bumps on adjacent chips. By positioning these frames at corner regions where bumps are located, the frames provide physical separation and electrical isolation, preventing direct contact between bumps from different chips. This eliminates the harmful effect of electrical shorts while maintaining the electrical connection functionality through properly isolated bump arrangements
Data Source
AI summary
A semiconductor package includes a plurality of semiconductor chips that face each other, a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips, an underfill layer that surrounds the plurality of bumps, and a plurality of insulating frames spaced apart from each other on the front or rear surface of one of the plurality of semiconductor chips. The plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other.