Stacked Semiconductor Package Layout for Crack-Resistant Die Bonding
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Solution Overview
Problem
In semiconductor package structures, misalignment of stacked memory chips leads to stress concentration and potential cracking at high-stress positions, particularly as the number of stacked tiers increases, due to uneven distribution of stress during die bonding.
Innovation Solution
The semiconductor device design includes a substrate with spacers positioned differently on the surface, where the first semiconductor chip is placed between these spacers, and additional memory chips are stacked with offsets, allowing the central position of the controller chip to be misaligned relative to the lowermost memory chip, thereby reducing stress and preventing cracking while maintaining a compact package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory chips are stacked with misalignment to expose metal pads for bonding wire connection, then ease of operation is improved, but stress concentration and cracking risk increase
Solution Approach 1:
The patent applies asymmetry by intentionally designing misalignment (offset) between stacked memory chips. The chips are positioned at different horizontal locations to expose metal pads for bonding wire access, creating an asymmetric stacked configuration that improves operational accessibility while managing stress distribution through controlled offset positions
2Productivity
If the number of stacked tiers is increased to improve integration density, then productivity is improved, but stress concentration and cracking risk increase
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacked configuration with controlled offsets. By utilizing the vertical dimension for stacking multiple tiers while introducing horizontal offset positions, the design achieves high integration density while distributing stress across different spatial levels, preventing concentration at single high-stress points
3Ease of operation
If misalignment offset is increased to expose metal pads, then ease of operation is improved, but stress concentration increases
Solution Approach 1:
The patent applies local quality by differentiating the offset positions for different stacked tiers. Rather than uniform misalignment, specific chips are positioned at specific offset locations tailored to their functional requirements - some tiers have larger offsets for pad accessibility while others have smaller offsets to reduce stress, creating locally optimized stress distribution across the stacked structure
Data Source
AI summary
A semiconductor device according to the present embodiment includes a substrate having a first surface, a first spacer and a second spacer, a first semiconductor chip, and a stacked body. The first semiconductor chip is provided on the first surface so as to be disposed between the first spacer and the second spacer. The stacked body is a stacked body that is provided above the first spacer, the second spacer, and the first semiconductor chip and in which a plurality of second semiconductor chips are stacked in a first direction. One of the second semiconductor chips, which is provided on the lowermost second semiconductor chip, is stacked with an offset relative to the lowermost second semiconductor chip in a second direction. A central position of the first semiconductor chip is separated from a central position of the lowermost second semiconductor chip in the second direction.