Stacked Semiconductor Package Layout for Crack Suppression
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Solution Overview
Problem
The challenge of preventing cracks in highly integrated semiconductor chips within semiconductor packages, while ensuring reliable connection and reducing production costs.
Innovation Solution
A semiconductor package design featuring a redistribution structure with a redistribution pattern and insulating layer, stacked semiconductor chips connected by conductive posts and molding layers, which are spaced apart to distribute stress and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked closely to increase integration, then device capacity and I/O connection terminals increase, but cracks occur on the semiconductor chips due to stress concentration
Solution Approach 1:
The patent divides the conductive connection structure into multiple separate conductive posts instead of a continuous structure. These posts are spaced apart to create stress relief zones, segmenting the stress distribution across the stacked chips while maintaining electrical connectivity. This segmentation prevents stress concentration that would otherwise cause cracks.
Solution Approach 2:
The patent introduces molding layers as intermediary structures between the stacked semiconductor chips. These molding layers act as stress-absorbing mediators that decouple the mechanical stress between adjacent chips, allowing the chips to be closely stacked for high integration while preventing direct stress transmission that would cause cracking.
2Volume of moving object
If conductive posts are placed close to semiconductor chips for compact design, then device size decreases, but stress concentration increases causing cracks
Solution Approach 1:
The patent applies different spatial arrangements to different regions: conductive posts are positioned close to chips in the horizontal plane for compactness, but are spaced apart in the vertical stacking direction to create stress relief zones. This local differentiation of spacing quality allows compact device volume while maintaining stress distribution strength.
3Temperature
If semiconductor chips are stacked with offset positioning to improve heat dissipation and stress distribution, then thermal management improves, but alignment precision and connection reliability become more difficult to maintain
Solution Approach 1:
The molding layer serves multiple functions simultaneously: it provides mechanical support for offset-stacked chips, enables thermal management by filling gaps for heat dissipation, and acts as an alignment reference structure. This multi-functionality allows offset stacking to achieve both thermal management benefits and maintained connection reliability.
Data Source
AI summary
A semiconductor package includes a redistribution structure, a first semiconductor chip above the redistribution structure, a second semiconductor chip on, and offset relative to, the first semiconductor chip, a plurality of first conductive posts extending from a bottom surface of the second semiconductor chip to a top surface of the redistribution structure, a third semiconductor chip on the second semiconductor chip, a plurality of second conductive posts extending from a bottom surface of the third semiconductor chip to the top surface of the redistribution structure, and a molding layer between the top surface of the redistribution structure and the bottom surface of the third semiconductor chip.