Stacked Semiconductor Package Wire Layout for Crosstalk Isolation
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Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining operating reliability and improving electrical properties due to crosstalk and interference between bonding wires, which affect signal transmission efficiency.
Innovation Solution
The semiconductor package design includes laterally spaced and insulated signal and power/ground pads, with bonding wires arranged to avoid direct overlap and interference, using redistribution layers to connect pads and wires, thereby preventing crosstalk and enhancing electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If bonding wires are placed closer together to reduce package size, then area is reduced, but crosstalk and interference between bonding wires increase
Solution Approach 1:
The patent introduces an intermediary structure (shielding pattern or ground wire) between adjacent bonding wires to prevent electromagnetic interference. This mediator absorbs or redirects electromagnetic fields, allowing bonding wires to be placed closer together without increasing crosstalk, thus reducing package area while maintaining electrical performance.
Solution Approach 2:
The patent adds a vertical dimension to the bonding wire arrangement by introducing shielding structures that extend in the vertical direction between bonding wires. This three-dimensional approach allows horizontal spacing to be reduced while the vertical shielding maintains electrical isolation, effectively resolving the area versus crosstalk contradiction.
2Productivity
If signal pads are placed closer together to increase density, then productivity is improved, but signal interference and crosstalk increase
Solution Approach 1:
The patent introduces ground pads or shielding structures as intermediaries between adjacent signal pads. These intermediary elements create electromagnetic shielding that prevents signal coupling between closely spaced pads, enabling higher pad density without sacrificing signal integrity or increasing interference.
Solution Approach 2:
The patent applies different local qualities to different regions of the package by placing ground shielding specifically between signal pads that are prone to crosstalk, while maintaining open areas where shielding is not needed. This localized approach maximizes signal pad density in critical areas while preventing interference only where necessary.
3Area of moving object
If bonding wires overlap vertically to reduce lateral space, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a molding compound as an intermediary material that encapsulates and stabilizes the bonding wires in their vertical overlap positions. This molding material provides mechanical support and precise positioning, reducing the tolerance requirements for wire placement while enabling compact vertical stacking arrangements.
Data Source
AI summary
Disclosed is a semiconductor package comprising a substrate that includes a plurality of substrate pads on a top surface of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, and a plurality of first bonding wires on a top surface of the first semiconductor chip and coupled to the substrate pads. The first semiconductor chip includes a first lower signal pad, a second lower signal pad laterally spaced apart from the first lower signal pad, and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad. One of the first bonding wires is coupled to the first lower signal pad. Any of the first bonding wires is not on a top surface of the second lower signal pad.