Stacked Semiconductor Package Layout to Prevent DAF Bleeding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The bleeding or regressing of Die Attach Film (DAF) during the stacking of semiconductor chips can lead to poor wire bonding connections, tilting, warping, or cracking of the upper semiconductor chip, resulting in decreased reliability and interference with metal wire connections.

Innovation Solution

A semiconductor device configuration featuring a circuit board with multiple resin layers, including a Non-Conductive Paste (NCP) and Die Attach Film (DAF), where the solder resist SR2 is selectively provided around the controller chip to reduce the thickness of the DAF and prevent bleeding, ensuring proper bonding and alignment of stacked memory chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the DAF is melted to bond semiconductor chips, then the bonding strength is improved, but the DAF bleeds or regresses from the chip end causing poor wire bonding connection

Engineering Contradiction:
Improvebonding strengthVSAvoidwire bonding connection quality
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The solder resist is selectively provided only around the controller chip rather than uniformly across all chips, creating local quality differentiation. This localized approach prevents DAF bleeding in critical areas while maintaining bonding strength where needed, and avoids interfering with wire bonding in pad adjacent areas.

Inventive Principle:
Principle #3Local quality

2Strength

If the DAF is melted to bond semiconductor chips, then the bonding strength is improved, but the upper semiconductor chip becomes tilted, warped, or cracked

Engineering Contradiction:
Improvebonding strengthVSAvoidchip structural integrity
Core Design Contradiction:
StrengthVSStability of the object's composition

Solution Approach 1:

The solder resist is provided beforehand around the controller chip to cushion and contain the DAF during the melting and bonding process. This preventive measure stops the DAF from causing tilting, warping, or cracking of the upper semiconductor chip by providing a barrier that manages the DAF's flow and expansion.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If the solder resist SR2 is selectively provided around the controller chip, then the DAF bleeding is prevented, but the device structure becomes more complex

Engineering Contradiction:
Improvebonding qualityVSAvoidresin layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The solder resist SR2 is selectively provided only around the controller chip rather than uniformly across the entire device, creating local quality differentiation. This localized application prevents DAF bleeding in critical areas while minimizing the addition to overall device complexity compared to a universal approach.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability of the semiconductor device by preventing resin bleeding, ensuring accurate wire bonding and maintaining chip alignment, thereby improving the embeddability and preventing voids and warpage of the circuit board.

Implementation Method 1

the DAF is melted to be embedded between the lower semiconductor chip and the upper semiconductor chip

Methodology Applied
Scientific EffectMelting: Melting

Implementation Method 2

one semiconductor chip is bonded onto another semiconductor chip on a lower tier via a DAF (Die Attachment Film)

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Implementation Method 3

the solder resist SR2 is selectively provided around the controller chip to reduce the thickness of the DAF and prevent bleeding

Methodology Applied
Scientific EffectPhysical barrier containment: Physical Containment

Data Source

PatentUS11837569B2Semiconductor device and manufacturing method thereof
Publication Date: 2023.12.05 KIOXIA CORP
  • US11837569B2 patent drawing
  • US11837569B2 patent drawing
  • US11837569B2 patent drawing

AI summary

A semiconductor device according to the present embodiment includes a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer. A first semiconductor chip is connected to a first one of the electrodes. A second semiconductor chip is provided above the first semiconductor chip, being larger than the first semiconductor chip, and is connected to a second one of the electrodes via a metal wire. A third resin layer is provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covers the first semiconductor chip.