Stacked Semiconductor Package Dams for Tilt and Short Prevention
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Solution Overview
Problem
Semiconductor packages face challenges in achieving structural reliability while being thin, light, and incorporating multiple semiconductor chips with improved functionality, as they are prone to tilting and short circuits during chip stacking.
Innovation Solution
Incorporating lower and upper dam structures on the semiconductor chips, along with an adhesive layer, to stabilize the stacking process and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked vertically to increase storage capacity and reduce package thickness, then the package becomes thinner and lighter with increased functionality, but the structural reliability deteriorates due to tilting and short circuit risks during stacking
Solution Approach 1:
The patent introduces an adhesive layer as an intermediary substance between the first and second semiconductor chips. This adhesive layer fills the gaps and irregularities at the interfaces between chips and substrates, providing mechanical bonding and preventing relative displacement or tilting during the stacking process, thereby resolving the contradiction between thin packaging and structural reliability
Solution Approach 2:
The patent applies the adhesive layer in advance before mounting the second semiconductor chip onto the first chip. This preliminary application of adhesive ensures proper positioning and prevents tilting during the subsequent mounting process, addressing the reliability issue before the stacking is completed while maintaining the thin package profile
Data Source
AI summary
A semiconductor package includes a first semiconductor chip; a lower dam structure disposed on an edge of a top surface of the first semiconductor substrate; a second semiconductor chip, which is mounted on the first semiconductor chip; an upper dam structure disposed on an edge of the bottom surface of the second semiconductor substrate; a chip connecting terminal disposed between the first semiconductor chip and the second semiconductor chip and connecting the first semiconductor chip to the second semiconductor chip; and an adhesive layer disposed between the first semiconductor chip and the second semiconductor chip and surrounding the chip connecting terminal.