Stacked Semiconductor Package Layout for Defect-Aware Chip Bonding
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Solution Overview
Problem
Existing multi-chip semiconductor packages face challenges in achieving compact size and high performance while minimizing waste and improving manufacturing yield, particularly due to the integration of defective chips.
Innovation Solution
A semiconductor package design featuring a multi-layer structure with redistribution layers and metal pillars connecting stacked semiconductor chips, along with a method to identify and avoid placing good chips over defective ones during manufacturing, ensuring efficient chip utilization and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-chip stacked package is used to achieve compact size and high performance, then functionality and integration are improved, but manufacturing complexity and difficulty in detecting defective chips increase
Solution Approach 1:
The patent applies preliminary action by performing electrical testing on chips before packaging and creating a wafer map that records the location of defective chips. This advance detection and documentation allows the manufacturing process to proactively avoid placing good chips over defective ones, thereby reducing manufacturing complexity and improving yield while maintaining the high functionality of multi-chip stacked packages.
2Productivity
If traditional multi-chip packaging is used without defective chip detection, then manufacturing process is simpler, but manufacturing yield and chip utilization are reduced due to waste from defective chips
Solution Approach 1:
The patent implements feedback by electrically testing chips, recording their status in a wafer map, and using this information to guide subsequent chip placement decisions. This feedback mechanism ensures that good chips are not wasted on defective chip locations, thereby improving manufacturing yield and chip utilization while maintaining relative simplicity in the manufacturing process.
3Quantity of substance
If good semiconductor chips are placed over defective chips, then chip utilization increases, but product reliability and performance are compromised
Solution Approach 1:
The patent applies the taking out principle by extracting or removing defective chips from the packaging process through advance electrical testing and wafer map creation. By identifying and excluding defective chip locations before good chips are placed, the system achieves high chip utilization while maintaining product reliability, as good chips are never placed over defective ones.
Data Source
AI summary
A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.