Stacked Semiconductor Package Structure for Chip Deformation Control
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved reliability due to the need for increased performance and capacity, particularly in three-dimensional structures where semiconductor chips are stacked.
Innovation Solution
A semiconductor package design that includes a package substrate with an insulating layer and interconnection layer, lower semiconductor chips spaced apart, connection wires connecting the chips, an adhesive layer covering the connection wires, an upper semiconductor chip, and an encapsulant filling the space between the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a three-dimensional structure with stacked semiconductor chips is used to increase performance and capacity, then the functional integration is improved, but the reliability deteriorates due to potential deformation and connection issues
Solution Approach 1:
The patent introduces an adhesive layer as an intermediary component between the lower semiconductor chips and the upper semiconductor chip. This adhesive layer serves as a mediator that not only bonds the chips together but also absorbs stress and prevents direct transmission of deformation forces, thereby maintaining reliability while enabling the 3D stacked functional integration.
Solution Approach 2:
The adhesive layer acts as a pre-established cushioning element between the stacked chips. By placing this compliant layer beforehand in the stacking structure, the patent prevents harmful stress concentration and deformation transmission before they can occur during operation or thermal cycling, thus preserving package reliability.
2Adaptability or versatility
If connection wires are used to electrically connect spaced-apart lower semiconductor chips, then the connectivity is improved, but the structural rigidity deteriorates due to the flexible wire structure
Solution Approach 1:
The patent merges the connection wire function with the adhesive layer by embedding the connection wires within the adhesive layer. This combination allows the rigid adhesive matrix to provide structural support and rigidity while the embedded flexible wires maintain electrical connectivity, thus resolving the contradiction between connectivity and structural strength.
Solution Approach 2:
The adhesive layer containing embedded connection wires forms a composite structure that combines the properties of the adhesive material (rigidity, stress absorption) with the conductive wires (electrical connectivity). This composite approach allows simultaneous achievement of structural rigidity and electrical connectivity.
3Adaptability or versatility
If lower semiconductor chips are spaced apart from each other, then the connection flexibility is improved, but the overall package rigidity deteriorates
Solution Approach 1:
The patent applies local quality by providing adhesive coverage at specific locations - the adhesive layer covers at least a portion of each connection wire and bonds the chips at critical interfaces. This localized adhesive application provides rigidity where needed for structural support while maintaining flexibility in other areas for connection adaptability.
Data Source
AI summary
A semiconductor package includes a package substrate including an insulating layer, an interconnection layer in the insulating layer, and interconnection pads on the insulating layer and electrically connected to the interconnection layer, first and second semiconductor chips on the package substrate and spaced apart from each other, first connection wires each extending from a first side of the first semiconductor chip to a second side of the second semiconductor chip and spaced apart from each other, an adhesive layer on the first and second semiconductor chips and covering at least a portion of each of the first connection wires, an upper semiconductor chip on the adhesive layer, second connection wires connecting the first and second semiconductor chips and the upper semiconductor chip to the interconnection layer of the package substrate, and an encapsulant on the package substrate and filling a space between the first and second semiconductor chips.