Stacked Semiconductor Package Structure for Interface Delamination
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving weight reduction, miniaturization, high performance, and high reliability, particularly in stacked semiconductor chip structures where delamination and adhesion issues occur at vulnerable interfaces.
Innovation Solution
A semiconductor package design that includes a base chip with lower bumps, stacked semiconductor chips, underfill layers surrounding the bumps, organic material layers contacting the semiconductor chips' edges, and an encapsulant covering the structure, which enhances adhesion and reduces delamination through the use of organic material layers to stabilize the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in multiple stages to achieve miniaturization and high capacity, then the density and capacity of the semiconductor package are improved, but the risk of delamination and adhesion failure at interfaces increases
Solution Approach 1:
The patent introduces an organic material layer as an intermediary between the bump and the semiconductor chip. This organic material layer acts as a mediator that improves adhesion at the interface, preventing delamination while maintaining the stacked chip structure. The organic material layer is disposed between the bump and the semiconductor chip, creating a stable bonding interface that resolves the adhesion problem inherent in multi-stage stacking.
Solution Approach 2:
The patent employs composite material structure by combining inorganic bump material with organic material layer. This composite approach creates a multi-material interface that leverages the advantages of both materials: the bump provides mechanical support and electrical connection, while the organic material layer provides adhesion and stress relief, together solving the reliability issue in stacked chip packages.
2Device complexity
If conventional stacking structures are used without additional adhesion layers, then the device complexity is reduced, but delamination occurs at the interface between bumps and semiconductor chips
Solution Approach 1:
The organic material layer serves as a mediator between the bump and semiconductor chip interface. Rather than adding complex multi-layer structures, this single organic layer acts as an effective intermediary that prevents delamination while maintaining relative structural simplicity. The organic material layer is specifically positioned at the critical interface where delamination occurs, providing targeted adhesion enhancement.
3Reliability
If the organic material layer is disposed between the bump and semiconductor chip to suppress delamination, then the interface adhesion is improved, but the manufacturing process complexity increases
Solution Approach 1:
The organic material layer is applied in advance to the bump surface before mounting the semiconductor chip. This preliminary action ensures that the adhesion-enhancing layer is already in place before the critical bonding step, making the manufacturing process more reliable. By preparing the interface beforehand with the organic material layer, the process becomes more controlled and less prone to delamination issues during subsequent steps.
Data Source
AI summary
A semiconductor package includes a base chip; semiconductor chips stacked on the base chip; bumps, a lowermost bump of the bumps disposed between the base chip and a lowermost semiconductor chip of the semiconductor chips, and each of the bumps except the lowermost bump respectively disposed between the semiconductor chips; organic material layers, a lowermost organic material layer of the organic material layers disposed between the base chip and the lowermost semiconductor chip, and each of organic material layers except the lowermost organic material layer respectively disposed between the plurality of semiconductor chips; underfill layers respectively surrounding the plurality of bumps, the underfill layers extending between the base chip and the lowermost semiconductor chip and between the semiconductor chips; and an encapsulant covering the base chip, the semiconductor chips, and the underfill layers.