Stacked Semiconductor Package Structure for Delamination Relief
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Solution Overview
Problem
Semiconductor packages experience delamination issues due to differences in thermal expansion coefficients between materials, leading to defects and degradation of thermal and electrical properties.
Innovation Solution
A semiconductor package design incorporating a buffer die, core die, and dummy die with specific bonding insulating films and metal patterns to alleviate delamination, using a hybrid copper bonding process with thermal compression and annealing to stabilize the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked to increase functionality and integration density, then the device complexity and functionality are improved, but warpage and delamination occur due to differences in coefficient of thermal expansion between materials
Solution Approach 1:
The patent introduces a dummy die with a metal pattern that has a different coefficient of thermal expansion than the substrate materials. This metal pattern is designed to generate compensatory stress during thermal cycling to counteract the warpage and delamination forces arising from stacking multiple semiconductor chips with different thermal expansion coefficients.
Solution Approach 2:
The invention utilizes the thermal expansion properties of materials by incorporating a metal pattern in the dummy die that expands or contracts at a different rate than the surrounding substrate during temperature changes. This differential thermal expansion creates internal stresses that compensate for the warpage and delamination caused by stacking multiple chips with mismatched thermal expansion coefficients.
2Productivity
If semiconductor chips are stacked in the same area to improve integration density, then the productivity and space utilization are improved, but thermal and electrical properties degrade due to delamination
Solution Approach 1:
The dummy die with metal pattern modifies the thermal and mechanical parameters of the stacked structure. The metal pattern's different thermal expansion coefficient creates compensatory stresses that maintain bonding integrity between chips, thereby preserving thermal and electrical properties while enabling high integration density stacking.
Solution Approach 2:
The metal pattern in the dummy die is designed to preemptively counteract the delamination and warpage forces that would otherwise occur during thermal cycling of the stacked chips. By introducing this compensatory mechanism in advance, the structure maintains its integrity and prevents degradation of thermal and electrical properties.
3Stability of the object's composition
If a buffer die is used to manage warpage in stacked semiconductor chips, then the structural stability is improved, but the device complexity increases due to additional components and bonding interfaces
Solution Approach 1:
The dummy die with metal pattern serves multiple functions: it acts as a structural support element, provides thermal expansion compensation, and serves as part of the bonding interface structure. This multi-functionality reduces the need for separate dedicated components, thereby managing structural stability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability and performance of semiconductor packages by minimizing delamination, maintaining structural integrity under varying thermal conditions.
Implementation Method 1
a warpage may occur due to a difference in coefficient of thermal expansion between the materials for forming the semiconductor chips
Implementation Method 2
using a hybrid copper bonding process with thermal compression and annealing to stabilize the structure
Data Source
AI summary
A semiconductor package includes a buffer die; a first core die on the buffer die; and a first dummy die on the first core die, wherein the buffer die includes: a first substrate including a first surface and a second surface; a first bonding insulating film on the second surface, wherein the first core die includes: a second substrate including a third surface facing the second surface and a fourth surface; and a second bonding insulating film that is in contact with the first bonding insulating film, wherein the first dummy die includes: a third substrate including a fifth surface facing the fourth surface and a sixth surface; a third bonding insulating film on the sixth surface; and a first metal pattern in the third bonding insulating film extending from a first corner region across a central portion of the first dummy die.