Stacked Semiconductor Package Substrates for Dense Stable Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller and more creative packaging techniques for semiconductor dies as demand grows for shrinking electronic devices, necessitating improved integration density and package stability.
Innovation Solution
The formation of stacked structures using multi-stack core substrates, where components are embedded within the substrate, enhancing rigidity and stability by bonding multiple core substrates together, and incorporating conductive routing layers and vias for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If multiple core substrates are bonded together to form stacked structures, then package stability and rigidity are improved, but device complexity increases
Solution Approach 1:
The package substrate is divided into multiple separate core substrates that are bonded together in a stacked configuration. Each core substrate can be independently fabricated and processed, then combined through bonding interfaces to form the complete package substrate structure, resolving the contradiction between stability and complexity
Solution Approach 2:
Multiple core substrates are nested together in a stacked arrangement where each substrate is positioned over the previous one, creating a multi-layer integrated structure. This nesting approach allows complex functionality to be achieved through systematic layering rather than a single complex substrate
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The fabrication process is segmented across multiple core substrates, allowing each substrate to be manufactured with standard precision requirements. The segmentation enables high integration density to be achieved through parallel processing of multiple substrates rather than requiring extreme precision in a single substrate
Solution Approach 2:
Instead of achieving integration density through lateral scaling (reducing feature size in two dimensions), the patent utilizes the third dimension by stacking multiple core substrates vertically. This dimensional transition allows high integration density without the exponentially increasing manufacturing precision demands of lateral scaling
3Volume of moving object
If electronic devices are shrunk to meet demand for smaller devices, then device size is reduced, but package functionality is compromised
Solution Approach 1:
The patent transitions from two-dimensional lateral scaling to three-dimensional vertical stacking to reduce device footprint. By arranging multiple core substrates in a stacked configuration, the package maintains rich functionality across multiple layers while achieving significant reduction in planar device size
Solution Approach 2:
Multiple functional components and interconnect structures are nested within the stacked core substrate architecture, allowing diverse package functionalities to be integrated in the vertical dimension while keeping the device's planar footprint small
Data Source
AI summary
A structure includes a first core substrate; an adhesive layer on the first core substrate; a second core substrate on the adhesive layer, wherein the second core substrate includes a first cavity; a first semiconductor device within the first cavity; a first insulating film extending over the second core substrate, over a top surface of the first semiconductor device, and within the first cavity; a through via extending through the first insulating film, the first core substrate, and the second core substrate; a first routing structure on the first core substrate and electrically connected to the through via; and a second routing structure on the first insulating film and electrically connected to the through via and the first semiconductor device.