Stacked Semiconductor Package Layout for Dense Wiring and Thin Profiles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in achieving high-density wiring on substrates while maintaining cost-effectiveness and reducing thickness and size, particularly in configurations with multiple semiconductor chips.
Innovation Solution
The semiconductor package design includes a frame with through-openings, multiple semiconductor chips stacked with overlapping configurations, bump patterns with dummy bumps, and posts connected via a redistribution layer, which allows for high-density electrical connections without increasing thickness, using a low-cost process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked in a package to increase capacity, then the quantity of chips per package increases, but the thickness and size of the package increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by stacking semiconductor chips vertically and using vertical posts to connect bump patterns across multiple chips. This dimensional change allows high-density interconnections without increasing package footprint or thickness, as connections are made in the vertical dimension rather than requiring lateral wire routing.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked one on top of another, with each chip containing bump patterns that are vertically aligned across chips. The posts penetrate through filling layers and connect corresponding bump patterns on different chips, creating a compact nested arrangement that maximizes chip density within the package volume.
2Productivity
If wiring density on substrate is increased to improve electrical connections, then the number of connections increases, but manufacturing complexity and cost increases
Solution Approach 1:
The patent segments the wiring function into discrete vertical posts that connect bump patterns on different chips. Each post is a separate, standardized element that can be manufactured independently and then assembled into the final package. This segmentation simplifies manufacturing compared to creating complex high-density lateral wire routing on a substrate, as the vertical connections are more straightforward to implement through alignment and bonding processes.
3Volume of moving object
If package thickness is reduced to meet size requirements, then the package becomes thinner, but heat dissipation capability deteriorates
Solution Approach 1:
The patent applies local quality by using filling layers with specific thermal properties in targeted regions between chips and around posts. These filling layers can be engineered to provide enhanced heat dissipation pathways in critical areas while maintaining overall package thinness. The localized application of thermally conductive materials allows heat management without sacrificing compact dimensions.
Data Source
AI summary
A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.