Stacked Semiconductor Package With Known Good Die Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging methods face challenges in efficiently integrating and testing semiconductor dies at the wafer level, leading to increased costs and reduced yield due to complex interfaces and lack of effective verification methods for 3D packaging and 3DIC devices.
Innovation Solution
A method for manufacturing semiconductor packages that involves dicing semiconductor wafers, testing and selecting known good dies, and using conductive pillars and insulating encapsulation to create a stacked structure with thermal dissipating elements, along with a redistribution circuit structure for electrical connectivity and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor wafers are diced and tested to select known good dies for 3D packaging, then manufacturing cost is reduced and yield is improved, but the integration process becomes more complex requiring conductive pillars, insulating encapsulation, and redistribution circuit structures
Solution Approach 1:
The patent segments the semiconductor manufacturing process into distinct stages: wafer-level testing to identify known good dies, separation of dies from the wafer substrate, and subsequent 3D stacking of selected dies. This segmentation allows for selective assembly of high-yield components while managing integration complexity through systematic process division.
Solution Approach 2:
The patent transitions from traditional 2D wafer-level integration to 3D stacked packaging architecture. By stacking multiple known good dies vertically using conductive pillars and insulating encapsulation, the solution achieves higher integration density and yield improvement while managing complexity through spatial reorganization rather than planar expansion.
2Reliability
If conductive pillars and insulating encapsulation are used to create stacked structures, then electrical connectivity and thermal management are enhanced, but the device structure and manufacturing process become more complex
Solution Approach 1:
The patent merges multiple functions into the insulating encapsulation material: electrical insulation between stacked dies, mechanical support for the 3D structure, and thermal conduction pathways. This consolidation reduces the number of separate components needed, thereby managing structural complexity while achieving reliable electrical connections and thermal management.
Solution Approach 2:
The conductive pillars serve multiple functions simultaneously: providing vertical electrical interconnect between dies, acting as thermal vias for heat dissipation, and serving as alignment features during the stacking process. This multi-functionality reduces the need for separate dedicated structures, managing overall device complexity.
3Productivity
If wafer level packaging is implemented for 3D packaging and 3DIC devices, then integration efficiency is improved, but manufacturing cost increases due to complex interfaces and lack of verification methods
Solution Approach 1:
The patent performs comprehensive testing and selection of known good dies at the wafer level before dicing and packaging. This preliminary action identifies and isolates defective dies early in the process, preventing their inclusion in the final 3D stacked product. This approach improves integration efficiency by ensuring only high-yield components are assembled, while the cost is managed through reduced rework and higher overall yield.
Solution Approach 2:
The patent implements a feedback mechanism where test results from wafer-level probing directly influence the selection of dies for 3D packaging. Known good dies are identified through test data feedback, and this information guides the subsequent assembly process. This feedback loop ensures high integration efficiency by preventing assembly of defective components, thereby reducing manufacturing costs associated with field failures and rework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves yield by simplifying the integration process, enhancing thermal management, and providing a reliable electrical connection within the semiconductor package.
Implementation Method 1
thermal dissipating elements
Data Source
AI summary
A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.