Stacked Semiconductor Package With Wiring-Free Dielectric Bonding
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Solution Overview
Problem
The demand for miniaturized and lightweight electronic components in portable devices necessitates the development of semiconductor packages that can integrate multiple devices into a single, reduced-size package while maintaining efficient connectivity and structural integrity.
Innovation Solution
A semiconductor package design featuring a stacked structure with dielectric layers and adhesive layers between semiconductor chips, where the dielectric layers are bonded without metal or internal wiring, and a molding layer surrounds the chip structure to enhance thickness reduction and prevent chip bending, allowing for thinner and more compact packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If multiple semiconductor chips are stacked with dielectric layers and adhesive layers, then the package thickness is reduced, but the structural integrity and chip stability may be compromised
Solution Approach 1:
The patent implements a stacked configuration where semiconductor chips are vertically arranged one above another, with each chip nested within a common footprint area. Multiple chips (first, second, and third semiconductor chips) are positioned at different vertical levels, effectively nesting functional elements in the Z-direction to reduce the lateral footprint while maintaining structural coherence through shared support structures.
Solution Approach 2:
The invention transitions from a planar arrangement to a three-dimensional stacked architecture. By utilizing the vertical dimension (Z-axis) for chip placement rather than expanding in the X-Y plane, the package achieves thickness reduction in the lateral dimensions while managing structural integrity through vertical support mechanisms and distributed loading across multiple bonding interfaces.
2Device complexity
If dielectric layers without wirings are used between chips, then the package complexity is reduced, but electrical connectivity between chips must be maintained through alternative means
Solution Approach 1:
The patent removes the wiring layer from the dielectric stack, extracting the traditional planar interconnect structure. Instead of embedding traces within the dielectric layers between chips, the design eliminates this intermediate wiring infrastructure, simplifying the layer stack and reducing manufacturing complexity while relying on direct chip-to-chip bonding interfaces for electrical connection.
Solution Approach 2:
The dielectric layers serve as mechanical intermediaries between stacked chips, providing structural support and insulation without performing electrical interconnection. The bonding pads and contact structures on chip surfaces act as the new intermediaries for electrical signal and power transfer, replacing the traditional dielectric-embedded trace architecture.
3Shape
If the molding layer surrounds the chip structure with coplanar outer walls, then the package shape is optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The molding structure is divided into distinct functional zones: a base portion supporting the chip stack and sidewalls extending upward to form outer walls. The sidewalls are configured to be coplanar with the sidewalls of the lower chips, creating a segmented geometric profile that simplifies tooling design and enables modular manufacturing approaches while achieving precise external dimensions.
Solution Approach 2:
The molding compound is applied in a controlled manner to form sidewalls that align coplanarly with chip sidewalls before final curing. This preliminary shaping of the mold cavity or pre-forming of the compound structure ensures that the outer walls naturally conform to the chip dimensions, reducing the need for post-molding precision adjustments and lowering manufacturing tolerance requirements.
Data Source
AI summary
A semiconductor package and method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip including first and second surfaces opposite to each other; connection terminals on the first surface of the first semiconductor chip; a first dielectric layer on the second surface of the first semiconductor chip; a second semiconductor chip on the first dielectric layer and including a third surface opposite to the second surface and a fourth surface opposite to the third surface; a second dielectric layer on the third surface of the second semiconductor chip and in contact with the first dielectric layer; a third semiconductor chip on the fourth surface of the second semiconductor chip; and a first adhesive layer between the second semiconductor chip and the third semiconductor chip, the first dielectric layer and the second dielectric layer including no wirings.