Stacked Semiconductor Package Layout for Direct Signal Paths
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in miniaturization, signal transmission performance, and cost reduction, particularly when dealing with semiconductor packages that require smaller and more complex configurations to meet demands for higher integration density, lower power consumption, and faster speeds.
Innovation Solution
The method involves stacking semiconductor dies with different sizes and using a hybrid bonding process, where the smaller die faces the ball array directly for improved signal transmission, and a redistribution layer structure is formed to connect the dies efficiently, allowing for direct signal transmission without additional routing or wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packaging techniques are used with traditional routing and wire bonding, then signal transmission paths are extended and package complexity increases, but signal transmission performance deteriorates and package size increases
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, where multiple semiconductor dies are vertically arranged and connected through through-substrate vias. This dimensional change allows direct vertical signal paths from the active die to the ball array, eliminating the need for complex lateral routing and wire bonding, thereby improving signal transmission performance while reducing package complexity.
Solution Approach 2:
The package is segmented into multiple functional semiconductor dies stacked vertically, with each die performing specific functions. The critical die with ball arrays is positioned at the bottom for direct external connections, while other dies are stacked above. This segmentation enables direct signal transmission from the critical die to external components without passing through other functional layers, reducing signal path length and improving performance.
2Quantity of substance
If minimum feature size is continuously reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision requirements increase and cost increases
Solution Approach 1:
Instead of continuing to reduce minimum feature size in the planar dimension, the patent utilizes the vertical dimension through stacked packaging. Multiple dies are stacked to achieve higher integration density without further reducing lateral feature sizes, thereby avoiding the increasing manufacturing precision requirements and associated cost increases that would result from continued feature size reduction.
3Volume of moving object
If smaller package size is achieved through miniaturization, then integration density increases, but signal transmission performance may deteriorate due to longer relative signal paths
Solution Approach 1:
The patent achieves miniaturization by stacking dies vertically rather than expanding laterally. The critical die is positioned at the bottom with direct vertical access to the ball array, ensuring that signal transmission paths remain short despite the reduced package footprint. This vertical arrangement maintains excellent signal transmission performance while achieving compact package dimensions.
Solution Approach 2:
The patent applies local quality optimization by positioning the critical die with ball arrays at the bottom of the stack, closest to the external connection points. This strategic placement ensures that the most performance-critical signals have the shortest possible transmission paths, while other functional dies can be arranged above without compromising signal performance. The package structure is locally optimized for signal integrity in the critical regions.
Data Source
AI summary
A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.