Stacked Semiconductor Package with Narrow Dummy Chip for Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in reliability due to limitations in compatibility and operating speed, particularly in the stacking and connection of semiconductor chips, which affect the overall performance and stability of electronic products.
Innovation Solution
The semiconductor package incorporates a first semiconductor chip stacked with multiple second semiconductor chips and a dummy chip, where the dummy chip has a smaller width and greater thickness than the second chips, enhancing the adhesiveness and structural stability through a mold layer and underfill layers, thereby improving the contact area and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked to increase operating speed and compatibility, then the functionality and performance are improved, but the reliability and structural stability deteriorate due to increased complexity and potential connection issues
Solution Approach 1:
The dummy chip is pre-configured with specific dimensional characteristics (smaller width, greater thickness) before stacking to proactively compensate for potential reliability issues that would arise from the multi-chip stacking configuration
Solution Approach 2:
The dummy chip's dimensions are specifically modified (width reduced to 0.1-0.9 times the first width, thickness increased to 1-3 times the first thickness) to change the structural parameters and improve reliability while maintaining the multi-chip stacking benefits
2Device complexity
If the dummy chip has smaller width to reduce structural complexity, then the device complexity is reduced, but the contact area and adhesiveness worsen
Solution Approach 1:
While reducing the width parameter to simplify structure, the thickness parameter is simultaneously increased to compensate for the reduced contact area, maintaining adhesiveness through parameter optimization
Solution Approach 2:
The combination of multiple underfill layers with different positions and the dummy chip creates a composite structure that enhances overall adhesiveness despite the reduced width of the dummy chip
3Reliability
If the dummy chip has greater thickness to improve structural stability, then the reliability is improved, but the manufacturing precision requirements worsen
Solution Approach 1:
The thickness parameter is optimized to a specific range (1-3 times the first thickness) that provides sufficient structural stability while remaining within achievable manufacturing precision capabilities
4Reliability
If underfill layers are added between chips to improve adhesiveness, then the reliability is improved, but the device complexity worsens
Solution Approach 1:
The underfill structure is segmented into three distinct layers positioned at different locations (first underfill layer at bottom, second underfill layer in middle, third underfill layer at top), with each layer serving a specific adhesive function, improving overall reliability through distributed reinforcement
Data Source
AI summary
Provided is a semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips on the first semiconductor chip, and a dummy chip on the plurality of second semiconductor chips, wherein each of the plurality of second semiconductor chips has a first width, and wherein the dummy chip has a second width smaller than the first width.