Stacked Semiconductor Package Using Dummy Solder Support
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in reducing size and weight while maintaining high electrical performance, particularly for high-frequency signal processing, with Through-Silicon Via (TSV) process technology being complex and costly.
Innovation Solution
A semiconductor package design featuring a first semiconductor chip mounted on a substrate with a conductive post and a second semiconductor chip stacked on the first chip, supported by dummy solder terminals and connected via signal solder terminals, with a mold layer encapsulating the structure to enhance stability and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV process technology is used to stack memory chips, then electrical connectivity and processing capacity are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the through-silicon via structure and replaces it with surface-level conductive posts on the substrate. This eliminates the need for complex TSV fabrication processes while maintaining electrical connectivity functionality through alternative means (conductive posts + solder terminals).
Solution Approach 2:
The patent uses dummy solder terminals that replicate the mechanical support function of actual electrical connections without requiring full electrical connectivity. This allows structural stabilization without duplicating the complex TSV electrical interconnection system.
2Volume of moving object
If multiple semiconductor chips are stacked to reduce size, then package dimensions are reduced, but structural stability becomes difficult to maintain
Solution Approach 1:
The patent segments the support function into two distinct components: conductive posts for electrical connectivity and dummy solder terminals for mechanical support. This segmentation allows each component to optimize its specific function without compromise, enabling stable multi-chip stacking in a compact package.
Solution Approach 2:
The conductive posts serve dual purposes: providing electrical connectivity pathways and acting as mounting structures for solder terminals. This multi-functionality reduces the need for separate support structures, maintaining stability while minimizing package volume.
3Ease of manufacture
If conductive posts are used instead of TSV, then manufacturing cost is reduced, but electrical connectivity for high-frequency signals may be compromised
Solution Approach 1:
The patent introduces solder terminals as intermediary elements that connect the second semiconductor chip to the conductive posts. This intermediary structure enables high-frequency signal transmission by providing optimized electrical pathways from the chip pads through the solder joints to the conductive posts, maintaining electrical characteristics comparable to TSV while using simpler manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces package size and weight, improves structural stability, and enhances electrical characteristics by optimizing the connection and support mechanisms between semiconductor chips.
Implementation Method 1
solder terminals connecting the conductive post to the second semiconductor chip
Data Source
AI summary
A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.