Stacked Semiconductor Package Substrate Layout for Edge Stress Relief
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Solution Overview
Problem
There is a challenge in increasing the integration and capacity of semiconductor devices while maintaining reliability, particularly in stacked semiconductor packages where defects in the package base substrate can occur, affecting the performance and durability of the devices.
Innovation Solution
A stacked semiconductor package design is introduced, featuring a package base substrate with top and bottom surface connecting pads, signal wires, and power wires, where the signal wires are strategically spaced to avoid stress concentrations and potential damage areas, and the substrate includes an overlap region with varying widths to accommodate different edge configurations of stacked semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signal wires are placed closer to the edge of the package base substrate to reduce area, then the area is reduced, but stress concentrations and potential damage occur
Solution Approach 1:
The patent applies local quality by creating different structural characteristics in different regions of the package base substrate. Specifically, the first region has a first width while the second region has a second width greater than the first width, allowing the substrate to have varying structural properties in different areas to balance area efficiency with stress resistance.
Solution Approach 2:
The package base substrate is segmented into multiple regions with different widths. The first region and second region are distinctly divided, with the second region providing enhanced structural support where stress concentrations are expected, while the first region optimizes for area efficiency.
2Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then the capacity is increased, but defects in the package base substrate affect performance
Solution Approach 1:
The patent implements beforehand cushioning by designing the package base substrate with a second region that has greater width and enhanced structural support in advance, before stacking the semiconductor chips. This pre-reinforced region is positioned to accommodate edge configurations and prevent stress concentrations that could lead to defects during or after the stacking process.
3Productivity
If the package base substrate is made smaller to improve integration, then integration is improved, but structural integrity is compromised
Solution Approach 1:
The patent applies local quality by creating different structural characteristics in different regions of the package base substrate. Specifically, the first region has a first width while the second region has a second width greater than the first width, allowing the substrate to have varying structural properties in different areas to balance area efficiency with stress resistance.
Solution Approach 2:
The patent addresses the strength-integration contradiction by transitioning to a multi-dimensional solution. Instead of uniformly reducing the substrate area in two dimensions, the patent varies the width in one dimension (creating regions with different widths) while maintaining the overall compact footprint, thus preserving structural integrity without sacrificing integration.
Data Source
AI summary
Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.