Stacked Semiconductor Package Layout for Through-Electrode Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a demand for high integration and miniaturization of semiconductor packages to reduce size and weight, particularly in portable electronic devices, while maintaining high-capacity data processing capabilities.
Innovation Solution
A semiconductor package is designed with a stacked chip structure, comprising a first semiconductor chip and a second semiconductor chip stacked on top of the first. The structure includes a semiconductor pattern spaced apart from the second semiconductor chip, an insulating gap fill pattern between the chips, and through-electrode structures that penetrate through the second semiconductor chip or the semiconductor pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If semiconductor chips are stacked vertically to reduce package volume, then volume is reduced, but manufacturing precision requirements increase due to alignment of through-electrode structures
Solution Approach 1:
The carrier substrate pre-forms multiple through-electrode structures at predetermined positions before the stacking process. This preliminary formation of conductive paths eliminates the need for precise alignment during subsequent chip stacking, as the through-electrodes are already positioned correctly in the carrier substrate. The method performs the complex alignment operation in advance during carrier substrate fabrication, which has better process control.
Solution Approach 2:
The carrier substrate acts as an intermediary component that receives multiple semiconductor chips and provides pre-formed through-electrode structures. Instead of directly aligning chips with each other (which requires high precision), the carrier substrate mediates the connection by providing its own pre-positioned through-electrodes that connect to bonding pads on different chips, thereby reducing the alignment burden.
2Quantity of substance
If multiple semiconductor chips are integrated in a single package, then integration capacity increases, but device complexity increases
Solution Approach 1:
The package structure is segmented into distinct functional components: a carrier substrate that provides mechanical support and pre-formed through-electrode structures, and multiple semiconductor chips that are independently mounted on the carrier. This segmentation allows each component to be optimized and manufactured separately, then assembled together, reducing overall system complexity despite high integration.
Solution Approach 2:
The carrier substrate serves multiple functions simultaneously: it provides mechanical support for the chips, establishes electrical connections through its through-electrode structures, and enables thermal management pathways. This multi-functionality consolidates several necessary components into one, reducing package complexity while maintaining high integration of multiple chips.
Data Source
AI summary
A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.