Stacked Package Structure Warpage Reduction via Elevated Connections
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Solution Overview
Problem
Conventional stacked package structures experience warpage and cold joints due to large substrate gaps and inefficient connection methods, leading to reduced reliability and increased costs.
Innovation Solution
A stacked package structure design featuring substrates with electrical connection devices higher than the chips, encapsulants covering these devices, and connection bumps that integrate the upper and bottom chip package structures, reducing substrate gaps and preventing warpage and cold joints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacked package structure is manufactured with large substrate gaps and outer region connections, then manufacturing process is simpler, but warpage and cold joints occur leading to reduced reliability
Solution Approach 1:
The patent transitions from planar connections at the outer region to three-dimensional connections by placing connection bumps on elevated electrical connection devices. This vertical dimensionality change allows connections to be made closer to the chip while avoiding the warpage and cold joint issues of conventional outer region connections.
Solution Approach 2:
The patent introduces electrical connection devices as intermediary structures between the chip and substrate. These devices serve as mediators that enable reliable electrical connection while mechanically bridging the gap between the chip and substrate, preventing both warpage and cold joint formation.
2Reliability
If chip package structures are connected at outer region with large substrate gaps, then manufacturing process is easier, but cold joints occur between structures
Solution Approach 1:
The patent performs preliminary action by pre-forming electrical connection devices on the substrate before chip attachment. This allows the connection structure to be prepared in advance with proper positioning and elevation, ensuring reliable connections without requiring complex real-time alignment during assembly.
Solution Approach 2:
The electrical connection devices act as intermediaries that simplify the connection process. By providing pre-formed connection points with elevated structures, the patent eliminates the need for complex outer region alignment and reduces the risk of cold joints during the bonding process.
3Manufacturing precision
If connection bumps are placed at outer region of substrates, then manufacturing is simpler, but warpage occurs in chip package structures
Solution Approach 1:
The patent uses vertical elevation of electrical connection devices to achieve precise alignment without requiring complex lateral positioning at the outer region. By moving connections to a different vertical level, the patent simplifies alignment while maintaining manufacturing precision.
Solution Approach 2:
The patent applies local quality by concentrating connection activities in specific localized regions around the chip rather than distributing them across the outer substrate region. This localized approach improves alignment precision while reducing the overall complexity of the connection structure.
4Area of stationary object
If conventional stacked package structure is used with large substrate area, then manufacturing is easier, but footprint area is large increasing PCB area
Solution Approach 1:
The patent transitions from two-dimensional substrate area to three-dimensional vertical stacking with elevated connection devices. This allows the package to achieve high connectivity in a compact footprint by utilizing the vertical dimension, thereby reducing the overall PCB area required while maintaining manufacturing feasibility.
Solution Approach 2:
The patent implements nesting by placing electrical connection devices and connection bumps within the footprint of the chip and substrate assembly rather than extending to the outer substrate region. This nested arrangement minimizes the overall package footprint while maintaining all necessary connection points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the yield and reliability of the stacked package structure by minimizing substrate area, reducing warpage, and preventing cold joints, thereby decreasing costs and improving manufacturing efficiency.
Implementation Method 1
a reflow step is performed, so as to connect the bumps 110 of the chip package structure 100 to the connection pads 216 of the chip package structure 200
Data Source
AI summary
A stacked package structure and a method for manufacturing the same are disclosed. The package structure comprises: a substrate having a first surface and a second surface in opposition to each other; at least one chip deposed on and electrically connected to the first surface of the substrate; a plurality of electrical connection devices deposed on the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude; and an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.