Stacked Semiconductor Package Layout for Low-Failure Fabrication
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Solution Overview
Problem
The semiconductor packaging industry faces challenges in developing compact, high-performance, and reliable semiconductor packages that integrate multiple chips within a single package, while maintaining high productivity and reducing fabrication failures.
Innovation Solution
A semiconductor package design that includes a redistribution substrate, multiple semiconductor chips, and insulating elements with varying material particle sizes, where the protection layers serve as stop layers in planarization processes, allowing for efficient fabrication and integration of chips with different sizes, and utilizing epoxy molding compounds for enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are integrated within a single package to reduce size and weight, then the compactness and integration density are improved, but the fabrication process complexity and failure rate increase
Solution Approach 1:
The patent divides the package structure into distinct segments: redistribution substrate, multiple semiconductor chips, insulating elements, and protection layers. Each segment serves a specific function and can be fabricated independently before assembly, thereby reducing overall fabrication complexity while achieving high integration density
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within the package, with lower chips positioned beneath upper chips. Insulating elements are nested between chips, and protection layers enclose the chips. This nesting approach maximizes space utilization, reducing package volume while maintaining manageable fabrication complexity through modular assembly
2Volume of moving object
If multiple semiconductor chips are integrated within a single package to reduce size and weight, then the compactness and integration density are improved, but the fabrication failure rate increases
Solution Approach 1:
The patent incorporates insulating elements positioned between semiconductor chips and between chips and the redistribution substrate. These insulating elements serve as cushioning components that prevent direct contact, reduce stress concentration, and provide isolation during thermal expansion and contraction, thereby preventing fabrication defects and reducing failure rates in multi-chip packages
Solution Approach 2:
The patent introduces insulating elements as intermediary components between conductive elements (chips, substrate, bumps). These intermediaries provide electrical isolation and mechanical buffering, preventing short circuits and reducing stress-related failures, thus improving overall package reliability
3Manufacturing precision
If protection layers with smaller particle size materials are used to enclose pads, then the manufacturing precision and electrical connectivity are improved, but the material cost and processing complexity increase
Solution Approach 1:
The patent applies different material properties to different regions: protection layers with smaller particle size materials are used specifically where high precision is needed (enclosing pads and conductive elements), while other regions may use different materials. This localized application of high-precision materials minimizes overall processing complexity while achieving necessary manufacturing precision at critical locations
Solution Approach 2:
The patent utilizes parameters such as particle size, material composition, and layer thickness to optimize both precision and manufacturability. By carefully controlling these parameters in protection layers, the patent achieves precise pad enclosure and good electrical connectivity while maintaining reasonable processing ease through optimized material selection and fabrication parameters
Data Source
AI summary
A semiconductor package may include a redistribution substrate, a first lower semiconductor chip on the redistribution substrate, an upper semiconductor chip on the first lower semiconductor chip, and a first insulating element between the redistribution substrate and the upper semiconductor chip to enclose the first lower semiconductor chip. The first lower semiconductor chip may include a first pad on a first surface of the first lower semiconductor chip, a first protection layer enclosing the first pad, a first penetration via that penetrates the first lower semiconductor chip and is electrically connected to the first pad, a second pad on a second surface of the first lower semiconductor chip facing the upper semiconductor chip, and a first insulating layer including the second pad. A particle size of a material including the first protection layer may be smaller than that of the first insulating element.