Stacked Semiconductor Package Adhesive Structure for Fillet Control
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Solution Overview
Problem
Current semiconductor packages with vertically stacked chips face challenges in achieving both small size and high performance, particularly in ensuring reliable connections and preventing excessive fillet formation during thermal compression, which can lead to defects and reduced reliability.
Innovation Solution
A semiconductor package design featuring a first semiconductor chip with multiple second chips stacked vertically, utilizing an insulating adhesive layer with distinct viscosity layers to prevent excessive fillet formation, where a first material layer with low viscosity surrounds chip connection terminals and a second material layer with higher viscosity prevents lateral flow and protrusion, and a molding layer covers the sides to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single viscosity adhesive layer is used during thermal compression, then the bonding process is simple, but excessive fillet formation occurs leading to defects and reduced reliability
Solution Approach 1:
The adhesive layer is segmented into two distinct material layers with different viscosities. The first material layer (lower viscosity) fills gaps and ensures intimate contact between chip surfaces, while the second material layer (higher viscosity) prevents excessive lateral flow and fillet formation. This segmentation resolves the contradiction by maintaining connection reliability through gap filling while avoiding defects through controlled flow limitation.
Solution Approach 2:
Different regions of the adhesive layer are assigned different viscosities to perform different functions. The first material layer with lower viscosity is applied in regions requiring gap filling and surface conforming, while the second material layer with higher viscosity is applied in regions where lateral flow control is critical. This local quality differentiation simultaneously achieves reliable bonding and prevents excessive fillet formation.
2Volume of moving object
If vertically stacked chip configuration is used, then package size is reduced, but connection reliability and structural integrity become more difficult to ensure
Solution Approach 1:
The adhesive system uses a composite structure of two materials with complementary properties. The first material provides flowability for gap filling and surface contact, while the second material provides structural support and flow control. This composite adhesive system enables reliable vertical stacking by ensuring intimate chip-to-chip contact while maintaining structural integrity during and after the bonding process.
3Strength
If thermal compression is applied to ensure good contact, then bonding strength is improved, but excessive fillet formation and lateral adhesive flow occur causing defects
Solution Approach 1:
The viscosity parameter of the adhesive layer is changed across different depths. The first material layer has lower viscosity to allow flow and gap filling under compression, while the second material layer has higher viscosity to resist excessive lateral flow. This parameter gradient enables the system to accommodate thermal compression forces, ensuring intimate contact and bonding strength while preventing excessive fillet formation and maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a compact, high-performance semiconductor package with improved reliability by preventing excessive fillet formation and ensuring stable connections between chips, thus enhancing the package's structural integrity and external appearance.
Implementation Method 1
a first material layer covering a sidewall of the chip connection terminal and having first viscosity
Implementation Method 2
a second material layer disposed to surround the first material layer in a plan view and have second viscosity which is greater than the first viscosity
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a front connection pad disposed on a lower surface of the plurality of second semiconductor chips, a rear connection pad attached on an upper surface of the first semiconductor chip and the second semiconductor chips, a chip connection terminal disposed between the front connection pad and the rear connection pad, and an insulating adhesive layer disposed between the first semiconductor chip and a lowermost second semiconductor chip and between two adjacent second semiconductor chips, the insulating adhesive layer including a first material layer covering a sidewall of the chip connection terminal and having first viscosity and a second material layer disposed to surround the first material layer in a plan view and have second viscosity which is greater than the first viscosity.