Stacked Semiconductor Package Layout for Fine-Pitch Chip Bonding
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving a compact design with fine pitch and low manufacturing costs, particularly when using printed circuit boards or interposers for electrical connections between multiple semiconductor chips.
Innovation Solution
A semiconductor package design that includes multiple device layers with through-electrodes and insulating layers, allowing for vertical overlap and electrical connection between semiconductor chips without the need for additional interposers or printed circuit boards, thereby reducing costs and achieving a smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a PCB is used for electrical connection between different types of semiconductor chips, then electrical connection is achieved, but fine pitch implementation becomes difficult
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the first and second semiconductor chips. This interposer substrate provides a fine-pitch connection interface that enables precise electrical connections without requiring the PCB to achieve fine pitch directly. The interposer acts as a mediator that transforms the connection requirements, allowing the main PCB to maintain its standard pitch while achieving fine-pitch connections at the chip level through the interposer's integrated circuit structures.
2Manufacturing precision
If an interposer is used for electrical connection between different types of semiconductor chips, then fine pitch connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple functions into the interposer substrate, including fine-pitch electrical connections, signal routing, and mechanical support. By combining these functions into a single integrated component rather than using separate PCB traces and connection structures, the overall manufacturing complexity is reduced. The interposer can be manufactured using standard semiconductor fabrication processes, which are more cost-effective for fine-pitch applications than custom PCB routing, thereby reducing overall manufacturing costs despite the addition of the interposer component.
3Ease of operation
If additional interposers and PCBs are used for electrical connections, then electrical connection between multiple semiconductor chips is achieved, but form factor increases
Solution Approach 1:
The patent transitions from a planar PCB-based connection architecture to a three-dimensional stacked architecture using the interposer substrate. The first and second semiconductor chips are vertically stacked with the interposer positioned between them, utilizing the vertical dimension (Z-axis) for electrical connections. This dimensional change allows multiple chips to be connected in a compact vertical arrangement rather than spreading them out horizontally on a large PCB, significantly reducing the overall form factor while maintaining full electrical connectivity.
Data Source
AI summary
A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.