Stacked IC Package with Flattened Interconnect
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in reducing size while maintaining performance and functionality, with existing solutions failing to simplify manufacturing, reduce electrical components on circuit boards, and enhance product features and reliability.
Innovation Solution
The method involves a base substrate with a base component connected directly to it, a stack component mounted over the base component, and a flattened exposed interconnect with an encapsulant applied, allowing a portion of the interconnect to be exposed, which reduces size and increases connectivity without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional integrated circuit packaging is used, then electrical connections and components can be established, but the package size and circuit board area increase
Solution Approach 1:
The patent implements a stacked package architecture where multiple integrated circuit packages are vertically nested one on top of another, sharing common circuit board footprint. The bottom package serves as a base substrate, and additional packages are mounted stacked above it, reducing the overall area required on the circuit board while maintaining multiple functional components.
Solution Approach 2:
The invention transitions from a two-dimensional layout of separate packages on a circuit board to a three-dimensional stacked configuration. By utilizing the vertical dimension (z-axis) to stack packages, the design reduces the horizontal footprint (x-y plane) on the circuit board while accommodating multiple components within the same area.
2Length of moving object
If package thickness is reduced to decrease size, then product compactness improves, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The patent employs preliminary underfill application between the stacked packages before final encapsulation. This underfill is applied in advance to provide mechanical support and stress relief to the thin package structure, preventing manufacturing defects and reliability issues that would otherwise arise from reduced package thickness.
Solution Approach 2:
The invention introduces an encapsulant as an intermediary material that surrounds and protects the stacked packages. This encapsulant provides structural support, mechanical protection, and environmental sealing, enabling the thin package design to achieve both compactness and manufacturing reliability by mediating between the fragile thin structure and external stresses.
3Adaptability or versatility
If more electrical connections are made between packages, then functionality and performance increase, but the number of electrical parts on circuit boards increases
Solution Approach 1:
The patent merges multiple separate package functions into a single stacked package assembly. Multiple integrated circuit packages that would traditionally require separate mounting locations and individual electrical connections to the circuit board are instead combined in a vertical stack, sharing a common footprint and reducing the total number of discrete electrical parts required on the circuit board.
Solution Approach 2:
The stacked package structure serves multiple functions simultaneously: it provides mechanical support for multiple components, establishes electrical interconnections between layers, offers environmental protection through encapsulation, and reduces overall footprint. This multi-functionality allows the single stacked assembly to replace what would otherwise require multiple separate components and connections.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; connecting a base component directly to the base substrate; mounting a stack component over the base component; attaching a flattened exposed interconnect directly on the stack component; and applying an encapsulant over the stack component with a portion of the flattened exposed interconnect exposed.