Stacked Semiconductor Package Adhesive Flow Barriers for Fine-Pitch Bumps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the manufacturing of system-in-package (SIP) with stacked chips, the reduced pitch between micro bumps increases the risk of solder sweep, leading to short circuits between adjacent micro bumps, which compromises the electrical reliability of the semiconductor package.
Innovation Solution
Incorporating flow prevention structures in the adhesive layer between the semiconductor chips, specifically in the test pad region, to reduce the flowability of the adhesive during the thermal compression process and prevent solder sweep between conductive bumps with fine pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch between micro bumps is reduced to increase the number of I/O terminals, then the I/O terminal density is improved, but the risk of short circuit due to solder sweep increases
Solution Approach 1:
The patent introduces a non-conductive film as an intermediary substance between adjacent conductive bumps. This film acts as a barrier that prevents solder material from sweeping across and causing short circuits, while allowing the pitch between bumps to remain reduced for high I/O density. The non-conductive film mediates between the conflicting requirements of small pitch and electrical isolation.
Solution Approach 2:
The patent converts the potentially harmful flow of adhesive material during thermal compression into a beneficial effect by strategically placing non-conductive films. The adhesive flow that would normally cause solder sweep is instead directed and contained by the non-conductive films, ensuring proper bonding while preventing short circuits. The harmful adhesive flow is transformed into a controlled process that maintains both low pitch and high reliability.
2Strength
If adhesive layer is applied between stacked chips, then the chips are bonded together, but solder sweep may occur between adjacent conductive bumps
Solution Approach 1:
The patent segments the bonding area by placing non-conductive films between adjacent conductive bumps. This segmentation divides the continuous adhesive layer into isolated regions, preventing solder material from flowing across bump boundaries while maintaining strong bonding within each segment. The segmentation strategy allows the adhesive to provide bonding strength without causing solder sweep.
Solution Approach 2:
The non-conductive film serves as an intermediary barrier between the adhesive layer and conductive bumps. During thermal compression, the film prevents direct contact between flowing adhesive and adjacent bumps, mediating the interaction to ensure bonding occurs without solder sweep. The intermediary film maintains both bonding integrity and electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of flow prevention structures effectively prevents short circuit failures due to solder sweep, thereby enhancing the electrical reliability of the semiconductor package by controlling the flow of the adhesive layer and maintaining the integrity of the conductive bumps.
Implementation Method 1
the adhesive layer is formed on the second wiring layer of the second semiconductor chip to cover the conductive bumps... The adhesive layer is on the first semiconductor chip so that the conductive bumps are disposed between the first bonding pads and the second bonding pads
Implementation Method 2
an adhesive layer between the first semiconductor chip and the second semiconductor chip to fill a space between the conductive bumps
Implementation Method 3
flow prevention structures in the adhesive layer, wherein the flow prevention structures are disposed in the test pad region... to reduce the flowability of the adhesive during the thermal compression process
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.