Stacked Semiconductor Package With Graded Dielectric Extensions
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Solution Overview
Problem
The increasing demand for high-performance, compact electronic devices has led to challenges in integrating multiple semiconductor chips within a single package, resulting in issues such as structural instability and increased failure rates due to the use of numerous adhesive members.
Innovation Solution
A semiconductor package design featuring a substrate with vias, stacked semiconductor chips, and non-conductive layers with varying protrusions and rigidity, where the distance from the substrate affects the length and rigidity of these extensions, and a method of fabrication involving thermocompression bonding, annealing, and selective etching to enhance structural stability and reduce failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are mounted in a single package using numerous adhesive members, then the integration density is improved, but the structural stability deteriorates due to warpage and delamination
Solution Approach 1:
The patent removes adhesive members from the packaging structure entirely, replacing them with direct mechanical interlocking through recesses and protrusions, and support structures that provide structural stability without adhesive-related warpage and delamination issues
Solution Approach 2:
The patent employs nested structures where recesses in upper chips accommodate protrusions from lower chips, creating interlocked stacked packages that maintain structural stability through geometric fitting rather than adhesive bonding
2Ease of manufacture
If adhesive members are used to attach semiconductor chips, then the mounting is improved, but the reliability deteriorates due to increased failure rates
Solution Approach 1:
The patent eliminates adhesive members from the mounting process, replacing chemical bonding with mechanical interlocking through recess-protrusion interfaces and support structures, thereby removing the source of adhesive-related failures
Solution Approach 2:
The recesses and protrusions are pre-formed on the chips before assembly, enabling reliable mechanical interlocking without requiring adhesives during the mounting process, thus preventing adhesive-related failures
3Ease of manufacture
If the non-conductive layer extensions are uniformly rigid, then the manufacturing is simplified, but the structural stability deteriorates due to warpage
Solution Approach 1:
The patent implements graded rigidity where the rigidity of non-conductive layer extensions varies by position - closer extensions have higher rigidity to prevent warpage at critical interfaces, while farther extensions have lower rigidity to accommodate thermal expansion and reduce stress
Solution Approach 2:
The patent changes the rigidity parameter of non-conductive layer extensions based on their distance from the substrate, creating a gradient structure that optimizes both warpage resistance and stress distribution across the stacked package
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design provides improved structural stability and reduced failure rates by minimizing warpage and delamination, while maintaining electrical connectivity and mechanical durability through the use of non-conductive layers with graded rigidity and selective etching.
Implementation Method 1
In the strip process, a first etch rate of the first extension may be less than a second etch rate of the second extension
Implementation Method 2
a method of fabricating the same may include providing a semiconductor wafer, providing a first non-conductive layer on the semiconductor wafer, providing a first semiconductor chip on the first non-conductive layer to mount the first semiconductor chip on the semiconductor wafer
Implementation Method 3
forming on the semiconductor wafer a molding layer that covers the first semiconductor chip and the second semiconductor chip
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.