Stacked Semiconductor Package Groove Layout for Adhesive Flow Control

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving miniaturization, weight reduction, high performance, and high reliability due to limitations in stacking semiconductor chips effectively, leading to issues with signal transmission and power distribution.

Innovation Solution

A semiconductor package design that includes a base chip with a substrate, upper protective layers, pads, and grooves, where semiconductor chips are stacked with bumps for electrical connection and an adhesive film fills the grooves to secure and smooth the adhesive flow during the pressure-reflow process, enhancing the reliability and efficiency of chip stacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor chips are stacked in multiple stages to achieve miniaturization and high performance, then the capacity and performance of the semiconductor package are improved, but the reliability and manufacturing precision deteriorate due to adhesive overflow and short circuits between bumps

Engineering Contradiction:
Improvechip stacking capacityVSAvoidpackage reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The upper protective layer is segmented by forming grooves that divide the adhesive application area into distinct regions. This segmentation prevents adhesive from spreading uncontrollably between stacked chips, thereby maintaining reliability while enabling multi-stage stacking for improved productivity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The groove structure creates local quality variations in the upper protective layer, with recessed areas (grooves) and elevated areas (pads). This local differentiation allows precise control of adhesive flow - adhesive is confined to specific local regions, preventing short circuits while enabling reliable multi-chip stacking

Inventive Principle:
Principle #3Local quality

2Strength

If adhesive is applied between stacked chips to fix the semiconductor chips, then the bonding strength is improved, but the manufacturing precision deteriorates due to adhesive overflow and short circuits between bumps

Engineering Contradiction:
Improvebonding strengthVSAvoidadhesive placement precision
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The grooves are formed in advance in the upper protective layer before adhesive application. This preliminary action creates pre-defined pathways and boundaries that guide adhesive flow, ensuring precise adhesive placement and preventing overflow that would compromise manufacturing precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The grooves act as intermediary structures between the adhesive and the bumps. They serve as a mediating element that controls adhesive flow, allowing the adhesive to fill the grooves and bond chips effectively while preventing direct contact between adhesive and bumps, thus maintaining manufacturing precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the reliability and efficiency of semiconductor packages by ensuring proper adhesive flow and reducing the risk of short circuits between bumps, thereby enhancing the performance and stability of the stacked chip structure.

Implementation Method 1

an adhesive film disposed between the base chip and the semiconductor chip, and fixing the semiconductor chip on the base chip

Methodology Applied
Scientific EffectAdhesive: Adhesive

Implementation Method 2

a bump disposed on the upper pad, and electrically connecting the base chip and the semiconductor chip

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20230402424A1Semiconductor package
Publication Date: 2023.12.14 SAMSUNG ELECTRONICS CO LTD
  • US20230402424A1 patent drawing
  • US20230402424A1 patent drawing
  • US20230402424A1 patent drawing

AI summary

A semiconductor package includes: a base chip including a substrate, an upper protective layer disposed on the substrate, an upper pad disposed on the upper protective layer, and a groove disposed adjacent to the upper pad and in which the upper protective layer is recessed; a semiconductor chip including a connection pad disposed on the upper pad, the semiconductor chip being mounted on the base chip; a bump disposed on the upper pad, and electrically connecting the base chip and the semiconductor chip; and an adhesive film disposed between the base chip and the semiconductor chip, and fixing the semiconductor chip on the base chip, wherein the adhesive film is configured to fill the groove.