Stacked Semiconductor Package Grooving Recess for Crack-Guided Dicing

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Solution Overview

Problem

Existing semiconductor chip singulation processes often result in damage to residual metal patterns and inter-wire insulating layers, leading to potential chipping and cracks, which compromises the reliability of the semiconductor chips and packages.

Innovation Solution

The implementation of a grooving recess structure in semiconductor chips and packages, featuring a first and second recess adjacent to the residual metal pattern, which guides crack propagation and prevents direct cutting during dicing, thereby protecting critical components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional singulation process is used to separate semiconductor chips, then productivity is improved through efficient chip separation, but residual metal patterns and inter-wire insulating layers are damaged causing chipping and cracks

Engineering Contradiction:
Improvechip separation efficiencyVSAvoidchip integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The grooving recess is formed in advance before the dicing process, creating a protective structure that guides crack propagation away from critical components. This preliminary structural preparation ensures that when dicing occurs, the cracks follow the predetermined groove path rather than damaging the metal patterns and insulating layers.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The grooving recess acts as an intermediary structure between the dicing blade and the critical components (metal patterns and insulating layers). It serves as a crack propagation path that intercepts and redirects the mechanical stress, preventing direct contact between the dicing process and the vulnerable components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If dicing is performed to separate stacked semiconductor packages, then productivity increases through batch processing, but cracks propagate damaging residual metal patterns and inter-wire insulating layers

Engineering Contradiction:
Improvebatch processing efficiencyVSAvoidstructural integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The grooving recess divides the package structure into distinct segments, creating a controlled separation zone. This segmentation allows the dicing process to cleanly separate packages along the groove without causing uncontrolled crack propagation that would damage the metal patterns and insulating layers across multiple chips simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The grooving recess converts the potentially harmful crack propagation during dicing into a beneficial controlled path. Instead of allowing random cracks to damage critical components, the groove provides a predetermined path that safely channels the mechanical stress, transforming the dicing-induced stress from a harmful factor into a controlled separation mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12355004B2Semiconductor chip and semiconductor package
Publication Date: 2025.07.08 SAMSUNG ELECTRONICS CO LTD
  • US12355004B2 patent drawing
  • US12355004B2 patent drawing
  • US12355004B2 patent drawing

AI summary

A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and an insulating adhesive layer between the first semiconductor chip, and each of the plurality of second semiconductor chips, each of the plurality second conductor chips, and the insulating adhesive layer including an adhesive fillet protruding from between at least the first semiconductor chip and each of the plurality of second semiconductor chips, wherein a grooving recess is defined by the first semiconductor chip, the plurality of second semiconductor chips, and the insulating adhesive layer, the grooving recess including a first recess and a second recess adjacent to the first recess, an uppermost surface of the adhesive fillet and the first semiconductor chip defines the first recess, and an uppermost surface of the first semiconductor chip to a surface inside the first semiconductor chip defines the second recess.