Stacked Semiconductor Package Layout for Heat and Adhesive Control
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization, increased performance, reduced weight, and high reliability while maintaining effective heat dissipation and electrical connectivity.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips with through-vias, bumps, dam structures, and insulating adhesive layers, including rear pads with line pads and dummy pads, and a bent-shaped dam structure to enhance heat dissipation and adhesive control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked in multiple layers to achieve miniaturization, then the package size and weight are reduced, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces through-vias that extend vertically through the stacked chip structure, creating a third-dimensional heat dissipation pathway. This allows heat to be conducted from upper chips down to the base chip and package substrate, effectively adding a vertical heat dissipation dimension that resolves the thermal management challenge in multi-layer stacked packages.
Solution Approach 2:
The patent introduces a thermal interface material as an intermediary substance between the base chip and package substrate. This material facilitates efficient thermal conduction from the stacked chips through the base chip to the package substrate, acting as a thermal mediator that improves heat dissipation without requiring direct metal-to-metal contact.
2Temperature
If the rear pad area is increased to improve heat dissipation, then heat dissipation performance is improved, but the available area for other components is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by implementing through-vias that conduct heat downward through the stacked structure. This allows heat dissipation to occur primarily through the vertical pathway via through-vias and base chip, rather than requiring extensive horizontal expansion of rear pads, thus preserving lateral area for other components.
Solution Approach 2:
The patent concentrates thermal conduction pathways at specific locations through strategically placed through-vias and thermal interface materials, rather than uniformly distributing heat dissipation structures across the entire package. This localized approach to thermal management allows efficient heat dissipation while maintaining overall package area efficiency.
3Reliability
If adhesive is applied extensively to ensure proper bonding, then bonding reliability is improved, but adhesive overflow onto pads causes electrical connectivity issues
Solution Approach 1:
The patent extracts the adhesive application area by defining specific adhesive application regions that exclude pad areas. The adhesive is applied only to designated regions on the package substrate, separating the bonding function from the electrical connection function, thereby preventing adhesive contamination of pads while ensuring adequate bonding.
Solution Approach 2:
The patent defines adhesive application regions in advance during the package design stage, clearly demarcating where adhesive should be applied before the actual bonding process. This preliminary definition of adhesive zones prevents overflow onto pads by establishing boundaries beforehand, ensuring both bonding reliability and electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves heat dissipation and reliability by increasing the metal proportion on the rear surface and controlling adhesive flow, thereby enhancing the overall performance and structural integrity of the semiconductor package.
Implementation Method 1
insulating adhesive layers at least partially surrounding the bumps and the dam structure
Implementation Method 2
the metal layers may include a first metal layer disposed on the rear surface of the base chip, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer
Data Source
AI summary
A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.