Stacked Semiconductor Package Layout for Heat and Interconnect Density
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration density and efficient thermal dissipation while maintaining a compact form factor, which limits their performance and scalability.
Innovation Solution
A semiconductor package configuration featuring a back-to-face or face-to-back structure with multiple die tiers and redistribution layers, utilizing high thermal conductivity materials and conductive pillars for efficient heat dissipation and reduced electrical paths, along with a method for forming redistribution structures and encapsulation layers to enhance connectivity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor package structures are used, then manufacturing simplicity is maintained, but integration density and thermal dissipation efficiency are insufficient
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to a three-dimensional stacked architecture with multiple die tiers (first die, second die, third die) arranged vertically. Redistribution layers are formed between tiers to enable electrical connectivity in the vertical dimension, thereby increasing integration density without proportionally increasing package footprint area.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple functional components are integrated within confined spaces: conductive pillars are embedded within redistribution layers, which are in turn embedded within encapsulation material, with multiple die tiers stacked within a single package body. This nesting enables high integration density by efficiently utilizing vertical space.
2Temperature
If conventional packaging is used, then package thickness is reduced, but thermal dissipation efficiency deteriorates
Solution Approach 1:
The patent employs composite material structures including encapsulation material with embedded conductive pillars, and redistribution layers combining conductive and insulating materials. These composite structures provide both mechanical support and enhanced thermal conduction pathways through the vertical stack, improving heat dissipation while maintaining compact thickness.
Solution Approach 2:
The patent introduces redistribution layers and encapsulation material as intermediary thermal management components between the active die tiers and the package exterior. These intermediaries provide continuous thermal conduction pathways that efficiently transport heat from internal heat-generating components to external heat sinks, resolving the contradiction between thin profile and effective thermal dissipation.
3Speed
If electrical paths are shortened for improved performance, then signal transmission speed increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the electrical interconnection path into discrete modular components: conductive pillars providing vertical inter-tier connections, redistribution layers providing lateral routing, and die-to-die interfaces. This segmentation allows each component to be formed and positioned independently with standardized processes, managing manufacturing precision requirements while achieving short effective electrical paths for high-speed signal transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration improves thermal dissipation and reduces electrical paths, enhancing the performance and scalability of semiconductor packages by allowing for higher integration density and reduced package thickness.
Implementation Method 1
utilizing high thermal conductivity materials and conductive pillars for efficient heat dissipation
Implementation Method 2
utilizing high thermal conductivity materials and conductive pillars for efficient heat dissipation and reduced electrical paths
Data Source
AI summary
A manufacturing method of a semiconductor package includes: covering a first die and a second die with a first insulating encapsulation; planarizing the first die, the second die, and the first insulating encapsulation, where a surface of the first insulating encapsulation is substantially leveled with surfaces of first die connectors of the first die and truncated spherical surfaces of second die connectors of the second die; and forming a first redistribution structure on the first insulating encapsulation, the first die and the second die. The first redistribution structure includes a dielectric layer and a conductive via in the dielectric layer and connected to a first portion of the truncated spherical surface, the dielectric layer is in contact with a second portion of the truncated spherical surface, and the second portion surrounds the first portion.