Stacked Semiconductor Package Heat Dissipation Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased demand for semiconductor chips with greater data storage capacity, functionality, and reduced size presents challenges with respect to heat dissipation.
Innovation Solution
A semiconductor package design featuring a heat dissipation structure on the upper semiconductor chip, connected to a rewiring layer through connection structures, with differing horizontal widths of the semiconductor chips and a co-planar arrangement to enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips with greater data storage capacity and enhanced functionality are implemented, then data storage capacity and functionality are improved, but heat generation increases and heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat dissipation by stacking multiple semiconductor chips vertically with heat dissipation structures between them. This dimensional change allows heat to be dissipated from multiple levels simultaneously, addressing the heat generation issue caused by increased data storage capacity without requiring proportional increases in planar area.
Solution Approach 2:
The patent introduces heat dissipation structures as intermediary elements between stacked semiconductor chips. These structures act as thermal mediators that conduct heat away from the chips, enabling high-density stacking while managing the thermal load generated by enhanced functionality and storage capacity.
2Volume of moving object
If semiconductor package size is reduced, then package size is improved, but heat dissipation efficiency deteriorates
Solution Approach 1:
The patent utilizes vertical stacking to achieve three-dimensional integration, reducing the horizontal footprint of the package while maintaining adequate heat dissipation capacity. By arranging chips and heat dissipation structures in multiple vertical layers, the design compactly packs functionality into a smaller volume without sacrificing thermal management effectiveness.
Solution Approach 2:
The patent divides the heat dissipation function into multiple segmented heat dissipation structures distributed across different vertical levels. Each structure handles heat from specific chips, allowing efficient thermal management in a compact, modular arrangement that reduces overall package size while maintaining heat dissipation efficiency.
3Productivity
If multiple semiconductor chips are stacked vertically to increase density, then integration density is improved, but heat accumulation increases
Solution Approach 1:
The patent segments the vertical stack into multiple functional layers with heat dissipation structures positioned between chips. This segmentation creates thermal pathways at each level, preventing heat accumulation by actively managing thermal load from each chip individually rather than allowing heat to build up in the entire stack.
Solution Approach 2:
The patent places heat dissipation structures as intermediaries between stacked chips, creating thermal management zones that prevent heat accumulation. These intermediary structures conduct heat away from each chip level, enabling high integration density while maintaining acceptable thermal conditions throughout the vertical stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively dissipates heat generated in the semiconductor chips, optimizing heat dissipation characteristics and enhancing operation speed and performance.
Implementation Method 1
a heat dissipation structure on the upper semiconductor chip... effectively dissipates heat generated in the semiconductor chips
Data Source
AI summary
A semiconductor package includes a first rewiring layer; a lower semiconductor chip on the first rewiring layer; an upper semiconductor chip on the lower semiconductor chip; a heat dissipation structure on the upper semiconductor chip; a molding layer on the first rewiring layer so as to contact side surfaces of the lower semiconductor chip, the upper semiconductor chip, and the heat dissipation structure; a second rewiring layer on the heat dissipation structure; and one or more connection structures on the first rewiring layer and positioned adjacent to the side surfaces of the lower semiconductor chip and the upper semiconductor chip and configured to extend through the molding layer and connect the first rewiring layer to the second rewiring layer, wherein the upper semiconductor chip and the heat dissipation structure contact each other.