Stacked Semiconductor Package with Vertical Heat Dissipation Paths
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, weight reduction, high performance, and reliability while maintaining effective heat dissipation and reducing manufacturing complexity and costs.
Innovation Solution
A semiconductor package design featuring multiple stacked semiconductor chips with through-electrodes and dummy electrodes forming a heat dissipation path, along with specific pad and interconnection configurations, to enhance thermal management and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of stationary object
If multiple semiconductor chips are stacked vertically to achieve miniaturization and weight reduction, then the package size and weight are reduced, but heat dissipation becomes more difficult due to limited thermal pathways
Solution Approach 1:
The patent introduces dummy electrodes extending in the vertical stacking direction to create additional thermal conduction pathways perpendicular to the chip stacking plane. This dimensional approach to heat dissipation allows thermal energy to escape vertically through the stack, overcoming the limited lateral thermal pathways in conventional stacked packages.
Solution Approach 2:
The patent segments the thermal management function by separating signal transmission (through standard through-electrodes) from heat dissipation (through dummy electrodes). This segmentation allows dedicated thermal pathways to be established without interfering with electrical signal integrity, addressing the heat dissipation challenge in multi-chip stacks.
2Reliability
If through-electrodes are used to electrically connect stacked chips, then electrical connection is achieved, but manufacturing complexity increases due to precise alignment requirements
Solution Approach 1:
The patent merges the functions of through-electrodes and dummy electrodes into a single fabrication process step. Both electrode types are formed simultaneously using the same plating process, reducing manufacturing steps and alignment complexity while maintaining reliable electrical connections through the dedicated through-electrodes.
Solution Approach 2:
The plating process used to form electrodes serves multiple functions: it creates both electrical connection pathways (through-electrodes) and thermal dissipation pathways (dummy electrodes) in a single operation. This multi-functionality reduces manufacturing complexity while ensuring reliable electrical connections.
3Temperature
If dummy electrodes are added to create heat dissipation paths, then heat dissipation characteristics are improved, but device complexity increases due to additional electrode structures
Solution Approach 1:
The patent combines the formation of through-electrodes and dummy electrodes into a single plating process step. By merging these operations, the patent adds heat dissipation functionality without proportionally increasing manufacturing complexity, as both electrode types are created simultaneously using the same process parameters.
4Reliability
If multiple groups of pads and through-electrodes are configured for efficient electrical connection, then connection reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments electrodes into through-electrodes (for electrical connection) and dummy electrodes (for heat dissipation), allowing each type to be optimized for its specific function. This segmentation enables reliable electrical connections through dedicated through-electrodes while simplifying the overall manufacturing process by using a unified formation approach for both types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves heat dissipation characteristics, reduces manufacturing complexity and costs, and ensures high reliability and performance by creating a structured heat dissipation path and efficient electrical connections between stacked chips.
Implementation Method 1
a plurality of through-electrodes penetrating through the substrate and electrically connected to at least one of the plurality of lower pads and the plurality of upper pads
Implementation Method 2
a plurality of interconnection bumps between the first semiconductor chip and the second semiconductor chip, the plurality of interconnection bumps electrically connecting corresponding ones of the first group of upper pads and the first group of lower pads
Data Source
AI summary
A semiconductor package includes electrically connected first to third semiconductor chips, stacked in a vertical direction; an encapsulant on the first semiconductor chip and encapsulating a portion of each of the semiconductor chips; and external connection bumps below the first semiconductor chip and being electrically connected to the semiconductor chips, wherein the semiconductor chips each include a plurality of lower pads, the first and second semiconductor chips each include a plurality of upper pads including a first group of upper pads and a second group of upper pads, and through-electrodes electrically respectively connecting the upper pads and the lower pads, and the through-electrodes include a first group of through-electrodes respectively connected to the first group of upper pads, and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads.