Stacked Semiconductor Package Layout for Planarization and Heat Dissipation
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Solution Overview
Problem
Challenges in 3DIC manufacturing include issues with surface roughness and unevenness due to pit formation in encapsulants, leading to potential connection failures and reduced integration density, as well as inadequate thermal dissipation and reliability in stacked semiconductor packages.
Innovation Solution
A method involving multiple passivation layers with planarization processes to achieve smooth surfaces, combined with a redistribution layer and an adhesive layer for thermal dissipation, ensuring precise alignment and improved connectivity between stacked integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple passivation layers with planarization processes are used to reduce surface roughness, then manufacturing precision and reliability are improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The encapsulant structure is segmented into multiple discrete passivation layers (first passivation layer, second passivation layer, third passivation layer) with distinct functions. Each layer addresses specific surface roughness issues at different stages, allowing systematic control of surface quality without requiring complete redesign of the entire encapsulation process.
Solution Approach 2:
Planarization processes are performed preliminarily at multiple stages during encapsulant formation - after each passivation layer is deposited, the surface is planarized before proceeding to the next layer. This preliminary planarization prevents accumulation of surface roughness and ensures consistent quality throughout the multi-layer structure.
2Productivity
If stacked integrated circuits are used to improve integration density, then productivity is improved, but thermal dissipation and reliability become inadequate
Solution Approach 1:
Thermal interface materials are introduced as intermediary layers between stacked integrated circuits and heat dissipation structures. These materials facilitate efficient thermal transfer across the interfaces, resolving the thermal dissipation bottleneck that typically limits stacked package reliability while preserving the high integration density benefits.
Solution Approach 2:
The patent transitions from planar heat dissipation to three-dimensional thermal management by implementing vertical heat dissipation paths through the stacked package structure. Heat sinks and thermal vias are positioned to conduct heat in the vertical dimension, enabling effective thermal management despite the increased integration density achieved through stacking.
3Productivity
If smaller feature sizes are used to improve integration density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter changes in the form of progressive planarization at multiple manufacturing stages. By controlling surface topology parameters (roughness, flatness) at each encapsulation stage, the process maintains manufacturing precision even as feature sizes are reduced to achieve higher integration density in stacked packages.
Data Source
AI summary
A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.